external clocks for FPGAs

[mush]

Hello all,

maybe it's a silly question but I can't understand the logic-functionality of external clocking. Why an FPGA needs so many different clocks and how someone defines the speed for each clock? E.g. I am planning to design a board using an FPGA which functionality is to serialize/deserialize data, sends them through an QSFP (GTPs @ 6.6Gb/s) and provides a number of external clocks (40, 80, 120, 160, 320MHz) to other boards. How many clocks do I need at all? Why I can't use one clock and increase/decrease it with the internal PLLs?

Does anyone know a book or something where I can find some info?

Any help would be appreciated!!

 

[barry]

An FPGA DOES NOT NEED more than one clock, but you are TELLING us that you need to provide 40,80, etc. Yes, you can use the resources of the FPGA to generate those output clocks from a single input clock.

 

[andre_luis]

Unless you must deal with some specific device which requires proper oscillator for generate precise timing, as barry already stated, just a single high frequency oscillator is enough for obtain all other clock phases.



+++

 

[mush]

Thank you for your prompt reply.

So, I have to use 2 or more clocks only if the frequency of the intrnal clock can't be produced from the input clock. (e.g. produce 90MHz from 200MHz input clock). Am I right? In the shematic of the evaluation board AC701 of Xilinx the FPGA handles 4 clocks (10 to 810MHz, 200MHz, 90MHz, 25MHz). Why doesn't the designer use the 200MHz to produce the 25MHz and vice versa?

If I use a precise clock source for my FPGA (e.g 40MHz) the output of the PLLs (80, 160, 320) isn't precise any more?

Thanks a lot

 

[barry]

You can't get exactly 90MHz from 200MHz, but you can probably get 88.9. Most FPGAs have PLL/DLLs that incorporate multipliers and dividers. Basically, you have:

fout=fin * M/N, where M and N are programmable.

When you use the internal PLL/DLL, you will add jitter to the clock, which is one reason not to use them. It all depends on your application.

 

[FvM]

You can't get exactly 90MHz from 200MHz.

Usual FPGA PLLs have pre- and postscaler. fout=fin * M/(N*C)
VCO 450 MHz, M=9, N=4, C=5

 

[barry]

Usual FPGA PLLs have pre- and postscaler. fout=fin * M/(N*C)
VCO 450 MHz, M=9, N=4, C=5

Right. The algebra part of my brain wasn't working today.

 

[mush]

So, in my case, I have an input clock of 40MHz, I have to increase the speed to 80 or 120 or 160 or 320MHz and distribute this clock to 16 boards through 2meters of differential cables. As you said, it is not a good idea to use the pll to increase the speed of the input clock and send the clocks through 32 standar IO pins of the FPGA but it's better to use the 40MHz clock as output from FPGA to the LMK03200 (0-Delay Clock Conditioner with 3LVDS ouputs) and then to CDCLV1208 2:8 buffer (low skew low jitter) and distribute them to the 16 boards.

 

[ads-ee]

I would suggest sending the 40 MHz to all the boards and using a local PLL on each board to generate the 80, 120, 160, and 320 MHz clocks. Sending 320 MHz clocks over 2m of differential cables isn't best practice. Besides the cost of good quality shielded differential cables will probably be more than the PLLs.

 

[mush]

Ads-ee, thanks for your comments. I am afraid we can't avoid the shielded cables... The 16 boards are already constructed and use ASICs. So, I don't know if the solution you mention is feasible. The point is that 320MHz is a fast speed for a differential cable?

 

[barry]

Ads-ee, thanks for your comments. I am afraid we can't avoid the shielded cables... The 16 boards are already constructed and use ASICs. So, I don't know if the solution you mention is feasible. The point is that 320MHz is a fast speed for a differential cable?

Gigabit Ethernet is sent over relatively inexpensive CAT5 cable, so you should be able to send 320MHz, but you are going to need to pay attention to termination, etc. You didn't mention distance...

 

[mrflibble]

Doesn't gbit work with a 125 MHz clock? It's probably still cheaper to generate the clocks locally (using a separate PLL module) from a boring low frequency like 40 MHz. As in the long cable run will transport 40 MHz, then go to your separate small PCB that accepts 40 MHz, and spits out the required clocks. Then with very short cable runs you go from your small PCB to your main PCB. The main cost will be time, but hey, small price to pay for not thinking up front. Then again, if you only need a few you could probably whip something up dead bug style in a few hours. After all, it's only 320 Mhz.

 

[mush]

We will use shielded cables anyway due to radiation. With that option, I think it's better to use 3 ICs (1 LMK03200 and 2 CDCLV1208 as mentioned before) than 16 PLLs and as you said, to send 16 clocks directly from the IO pins of the FPGA is not a good practice, it's seems to be the better choice.

 

[barry]

Doesn't gbit work with a 125 MHz clock? )

Accch, you're right. Forgot about that. Still, I think sending 320MHz over a cable shouldn't be TOO difficult if that's what the OP really wants.

 

[ads-ee]

Doesn't gbit work with a 125 MHz clock?

It also uses 5-level signalling to encode the symbols and TCM over the 4 pairs.

Still, I think sending 320MHz over a cable shouldn't be TOO difficult if that's what the OP really wants.

Yeah it can be done, but I just wouldn't recommend it for anything that would be fielded. One off for POC, yeah fine. Production units, no freaking way! (unless you hate your field and service reps ;-))

Seems that the systems design fell short on this project. I would have insisted on 40 MHz across the cables and PLLs at the destinations to generate all the clocks.

regards

 

[barry]

You can send GHz signals over cable (it's done with radar systems all the time).

 

[TrickyDicky]

They are usually differential signals with low impedance cables and plenty of shielding.

 

[barry]

They are usually differential signals with low impedance cables and plenty of shielding.

Except when they're coaxial cables that run well up into the tens of GHz.

 

[mush]

I would have insisted on 40 MHz across the cables and PLLs at the destinations to generate all the clocks.

regards

I still cannot understand the reason of using 16 plls and a 40MHz clock instead of 1 pll and 320MHz clock. As dear colleagues said before, we excluded the option to send 16 clocks out of the standar IO pins of the FPGA because PLL impose jitter. Also, I found out that differential cables were tested@ about 5GHz with no problem.