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[SOLVED] External clock generation scheme vhdl code??

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deepthi.reddy.912

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Is there any external clock generation scheme available in Xilinx ISE or in ModelSim or any sample vhdl code for providing synchronous clock for all pipelined stages in a combinational circuit? If so please help me.
 

rhaynes

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Something like this???

signal i_clk : std_logic := '0';

process(i_clk)
begin
i_clk<= not i_clk after 10 ns;
end process;
 

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