[SOLVED] External clock generation scheme vhdl code??

[deepthi.reddy.912]

Is there any external clock generation scheme available in Xilinx ISE or in ModelSim or any sample vhdl code for providing synchronous clock for all pipelined stages in a combinational circuit? If so please help me.

 

[rhaynes]

Something like this???

signal i_clk : std_logic := '0';

process(i_clk)
begin
i_clk<= not i_clk after 10 ns;
end process;