Exploiting the parallel nature of FPGA to implement Sorting Algorithms

[electrobuz]

I want to implement basic Sorting Algorithms in VHDL. I have done so and found out how ineffective a serially executing program (having loops and processes) can be. Now I would like to exploit the parallel nature of FPGA to do the same in a more efficient and time-saving manner. How can I go about deciding how to parallelise the code. Can someone suggest some reading material on parallel programming in VHDL.

Thank You

 

[FvM]

As a starting point, you may want to google for "sorting networks in FPGA"

 

[electrobuz]

As a starting point, you may want to google for "sorting networks in FPGA"

Thank you for the start. As I was reading I came across a concept called Hardware Software Co-design. I think this relates to effective parallelisation. Thinking in terms of smaller logical blocks instead of the loops is a way indeed but can I use the above concept. That is dividing the program in a way to use the resources of both parallel and serial parts. Can I get some help in this direction?

 

[FvM]

Co-design presumes that beside the FPGA hardware there's a software component in the design, e.g. a processor. That's quite different from implementing an algorithm purely in FPGA hardware.

 

[electrobuz]

I understand the difference. But what do you really mean by a software component? How can I partition one program to run on 2 different devices to give me a combined result?

 

[mrflibble]

Same way as always. You can have a processor and a co-processor. The main processor would be your main cpu/mcu. And the co-processor doing some specialized task (in this case sorting, either in part or in whole) would be done by the fpga.