VHDL was designed to be a MULTIPURPOSE simulation language . But this days is used to do synthesis also .Is a language that has been revised and augmented in PRIMITIVES .
SO the coding style depends wheather you use it FOR SIMULATION or SYNTESIS .
Simulation is STRAIGHT FORWARD ..
Synthesis is a little TRICKY because for example the language has no CONCEPT of REGISTER .. so it has to be IMPLIED .! , Most SYNTHESIS tools now have more or less agreed how to do this ,.But this is SOMETHING that you need excersize .
The language is very rich and it takes some time to be able to deal with its different types ..but i love it!
Explicit state machines are a direct translation of the hardware: a concurrent assignments for the next-state equations and a clocked process for the flops to hold the state. Explicit state machines are more cumbersome to write, but they are simpler to synthesize and more commonly used.
Implicit state machines are built with processes that have multiple wait statements in a process. Implicit state machines are concise and readable.
If you do logic synthesis, you can find piles of documents on synthesis coding style from EDA vendors, and if you are interested in behavior coding style to write testbenches for simulation and verification, you can read books like "writing testbenches by Janick Bergeron" for further steps.