Explanation of VHDL data types and their usage

[cyboman]

since i'm somewhat new to digital design and code in verilog i decided to take a look at vhdl. as far as i understand it is a very strongly typed language.

i understood that signals of type std_logic and std_logic_vector can take on the values of 1, 0, u, x, and z, but what about the following types

unsgined
signed
natural
integer
boolean

for that matter, since any hdl is used to model a digital circuit why do we need so many types of variables? aren't all of them just boolean type? maybe someone can give an example where i would use singed type as opposed to std_logic or unsgined as opposed to std_logic_vector

any help is appreciated

 

[FvM]

Re: vhdl data types

for that matter, since any hdl is used to model a digital circuit why do we need so many types of variables?

The different types actually serve a purpose. To understand their possible benefit, you should consider, that digital logic can be used
also for signal processing applications, involving e.g. arithmetic operations. An important feature of a high level hardware
description language is the capability to describe the intended operation exactly as intended. If you want e.g. signed arithmetic, you
can write result <= a*(b+c);, using signals of signed type. On the hardware level, signed and unsigned are equivalent
to bit vectors (std_logic_vector type) of the same length, but they have associated specific operators and functions.

Integer and it's subtypes (e.g.natural) are more abstract types, also real. They are mostly used for parameters and compile time
calculations. But an integer signal with a range specification is also a synthesizable type, that can be used instead of or in combination
with signed and unsigned.

If you consult one of many available VHDL text books, you'll find many useful applications of the said data types. A book,
that has many examples of signal processing arithmetic is U. Meyer-Baese, Digital Signal Processing with Field Programmable
Gate Arrays.

 

[cyboman]

Re: vhdl data types

FvM,

so what would be the difference between the following implementations

a, b, c: std_logic_vector(7 downto 0);
result: std_logic_vector(15 downto 0);

result <= c*(a + b);

a, b, c: unsigned(7 downto 0);
result: unsigned(15 downto 0);

result <= c*(a + b);

a, b, c: signed(7 downto 0);
result: signed(15 downto 0);

result <= c*(a + b);

the result is still a collection of 0's and 1's. will the synthesizer use different kind of adders and multipliers if it is signed math? if it is then next question would be what is the difference between std_logic, unsigned and boolean? it seems to me that they are all unsigned.

 

[Dreamer_Bl]

Re: vhdl data types

Cyboman,

Actually you are right. At the end all will be '0's and '1's. Before the end. When you are describing your idea/comcept on a abstrect level then is really useful if you have predefined functions for example with signed or unsigned variables. Then it is much faster and easier to describe your idea. Can you get it? ... dealing with the sign is covered by those functions, so for you there should be only a remainder about the total bits you are working with - 16 signed - 1 bit for sign and 15 data bits ... and 16 bits unsigned - 16 data bits

On the other side, by using std_logic you can experience states like "Z", "U" and "X" during your simulations ... which is useful when you are debuging your concept/design