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for top, it means all net use the same wireload as which used on the top level, so the wireload used on hierarchical cells has no effect. if you used the flattend design to layout, you can chose this mode;
for enclosed,it means the wire load models on hierarchical cells are used to calculate in nets inside these blocks. net values are determined using the wire load model of the hierarchical cell which fully encloses the net. if you logical and physical hierarchy are similar after layout, you can chose this mode;
for segmented,it means segments of the net in each level of hierarchy are calculated separately, and the net value is the total of all segments.
Hierarchical boundary pins are included in the pin count for the segment, this mode need the tech lib provide the Segmented wire_load, so it's often not used .
Consider the design as it has no hierocracy and use the WLM for the top module to calculate delays for all modules.
Any low level WLM is ignored.
Use the WLM of the module which completely encloses the net to compute delay for that net.
If a net goes across several WLM, use the WLM that corresponds to that portion of the net which it encloses only.