Explanation of Latch-up in MOSFET gate driver

[dohzer]

I'm a bit confused by an explanation I found in a Fairchild Application note: AN-6076 - Design and Application Guide of Bootstrap Circuit for Hign Voltage Gate-Drive IC
Specifically, page 3 at Fig. 9 and Fig. 10, and the explanation of why Dbs conducts.


I can understand the "example" part, but not the explanation above it.
The example suggests that the bootstrap capacitor exceeds the Dbs breakdown voltage, and it dies. I can understand this.
The explanation text before it talks about Dbs conducting which causes overcharging of the capacitor... but how can it charge if Dbs conducts. Wouldn't that limit Vbs (and therefore the capacitor voltage) to the diode's forward voltage drop? And regardless of this, if Vs is below Vb, how can Dbs conduct? Is it conduction via reverse breakdown?

 

[FvM]

The example suggests that the bootstrap capacitor exceeds the Dbs breakdown voltage

Not at all. The text is talking about latchup, not overvoltage. Latchup is triggered by forward biasing IC junctions that are part of parasitic (unwanted but unavoidable) thyristor structures.

In this case undershoot of the Vb (and subsequently Vs) node relative to COM forward biases the Vs substrate diode. If the current exceeds the latchup threshold, a supply short with chip failure can result. Refer also to the IRF application notes for a detailed explanation, e.g. http://www.irf.com/technical-info/designtp/dt97-3.pdf

 

[dohzer]

Refer also to the IRF application notes for a detailed explanation, e.g. http://www.irf.com/technical-info/designtp/dt97-3.pdf

Thanks for that; I'll read it when I get a chance.

Not at all. The text is talking about latchup, not overvoltage. Latchup is triggered by forward biasing IC junctions that are part of parasitic (unwanted but unavoidable) thyristor structures.

The text/example is talking about latch-up and the risk of overvoltage. It says that the capacitor can be overcharged, causing failure of the parasitic diode.

In this case undershoot of the Vb (and subsequently Vs) node relative to COM forward biases the Vs substrate diode. If the current exceeds the latchup threshold, a supply short with chip failure can result.

They don't actually mention COM in this part other than to say Vs goes negative relative to it. They discuss conduction from Vs to Vb. But that would require Vb to be below Vs (at least the way they have drawn it). How does Vb get lower than Vs?

In the example following this one, they start talking about conduction from COM to Vb because of excessive undershoot.

 

[FvM]

You are right, the substrate diode is between Vb and COM. It's forward biased, if Vs swings more than |Vbootstrap| below COM. That's the critical case discussed in all application notes.

Besides causing latch-up, the undershoot can potentially charge the bootstrap capacitor to overvoltage.