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Explanation of ESD and Latch-up in layout design

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blueant

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about ESD and Latch-up

I am a new layout designer, anybody can explain about ESD and Latch-up, or recommend books.
Very thanks
 

Re: about ESD and Latch-up

In ESD refers to an overvoltage transient that is caused by static charge. The overvoltage can be caused by conducted or coupled charge.

Conducted charge is caused by actual contact from a voltage source (test equipment, manufacturing equipment, or people are common sources of ESD conducted charge)

Coupled charge can cause problems without actual contact. An electric field in proximity to your circuit can cause charge to be redistributed in the circuit, and can cause charge buildup in some areas of the circuit that could cause damage.

If the resulting charge buildup is not sufficiently disbursed, it can cause high voltage on components. This can cause breakdown within your circuit, which can cause damage. The damaged part can cause a hard failure (fails immediately) or can cause a latent failure (part is damaged, but continues to operate for some time before completely failint) ESD protection circuits are used to disperse the charge along known pathways that are resistant to damage.

Latch-up is a condition where a circuit goes into a high current state that can only be eliminated by removing the current. Typically for latch up, a parasitic SCR is triggered, and the positive feedback within the SCR causes high current to flow, even as the voltage drops. Layout techniques are often used to minimize the risk of latch up. The most common things are the use of guard-rings and low impedance substrates. Both of these things act to reduce the positive feedback. If the feedback is sufficiently reduced, the SCR will no longer be able to remain active, and latch-up will not occur.
 
Re: about ESD and Latch-up

JPR's explanation is very clarity, JPR is very good!
 

Re: about ESD and Latch-up

ESD in silicon integrated circuit
 

about ESD and Latch-up

pls. refer to the art of analog layout
 

Re: about ESD and Latch-up

well explained in art of analog layout book
 

Re: about ESD and Latch-up

use contact to substrate to decrease the res
 

about ESD and Latch-up

thank you JPR
thanks anybody
 

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