Explanation about ETS Timing Report

[Gautam Nani]

Initially I ran the timing report for parent and child blocks sperately and finally ran the flat timing. The results that I got for the parent and child blocks is totally different from the flat timing. my doubt is when I ran the timing report for the parent block, that itself contains the child block in it. so why the results of parent block is different from flat timing.

Please explain these terms in timing report

Path 1: VIOLATED Setup Check with Pin XXXXX/reg/CK
Endpoint: xxxx/reg/D (v) checked with leading edge of 'CLK'
Beginpoint: XXXX/reg/Q (v) triggered by leading edge of 'CLK'

Path Groups: {reg2reg}

Analysis View: this is at typical m40
Other End Arrival Time xxxx
- Setup xxxx
+ Phase Shift xxxx How should i interpret this phase shift?
+ CPPR Adjustment xxxx What is CPPR. Is this Clock reconvergence pessimism removal?
- Uncertainty xxxx what is this uncertainity?
= Required Time xxxx
- Arrival Time xxxx
= Slack Time xxxx
Clock Rise Edge xxxx
+ Clock Network Latency (Prop) xxxx
= Beginpoint Arrival Time xxxx

Thanks in advance,
-Gautam

 

[Gautam Nani]

Initially I ran the timing report for parent and child blocks sperately and finally ran the flat timing. The results that I got for the parent and child blocks is totally different from the flat timing. my doubt is when I ran the timing report for the parent block, that itself contains the child block in it. so why the results of parent block is different from flat timing. Could you please explain this?

 

[ads-ee]

Let's see if I can help.

I'm assuming the issues are with the -/+ values used in the timing report?

- Setup xxxx
destination setup time means that we remove that time from the period, as the signal needs to arrive that much earlier than the clock edge at the destination.

+ Phase Shift xxxx How should i interpret this phase shift?
phase shift means there is clock skew between the source and the destination registers, positive skew means the destination clock arrives later than the source clock. i.e. we add the skew to the period

+ CPPR Adjustment xxxx What is CPPR. Is this Clock reconvergence pessimism removal?
I think it stands for Common Path Pessimism Removal. You can look at this explanation (basically removes common clock tree elements from the calculations for clock skew)

- Uncertainty xxxx what is this uncertainity?
this is the clock uncertainty, i.e. the clock period jitter. It's subtracted because it can reduce the period when the edges of a clock are closer together.[/]

= Required Time xxxx
this is when the signal needs to be at the register if you want it to meet setup time.

- Arrival Time xxxx
this is when the signal will arrive at the register based on the path delay from the source to the destination

= Slack Time xxxx
say if your period was 10 ns but the setup+phase_shift+cppr+uncertianty ended up as -3 ns then the data is required in 7 ns (10-3). If the data path delay is only 2 ns then you'll have a +5 ns slack, i.e. it passes timing. If the data path delay was 10 ns then you would have a -3 ns (7-10) slack, i.e. fails timing.

Clock Rise Edge xxxx
+ Clock Network Latency (Prop) xxxx
= Beginpoint Arrival Time xxxxv
not entirely sure what this is supposed to be in this timing report.[//i]

- - - Updated - - -

Initially I ran the timing report for parent and child blocks sperately and finally ran the flat timing. The results that I got for the parent and child blocks is totally different from the flat timing. my doubt is when I ran the timing report for the parent block, that itself contains the child block in it. so why the results of parent block is different from flat timing. Could you please explain this?

How was hierarchy removed? If a flattened design is just a removal of the hierarchical boundaries to make everything flat then timing shouldn't change. If flattening is optimizing logic across the boundaries, you'll end up with different results.

As I don't know the ETS tool I have no idea.

 

[Gautam Nani]

Could you please explain why the phase shift & cppr are being added and why uncertainity is being subtracted to get required time? how should I interpret negative clock network latency? what is end arrival time. Is it the delay of the capture clock path?

Let's see if I can help.

I'm assuming the issues are with the -/+ values used in the timing report?

- Setup xxxx
destination setup time means that we remove that time from the period, as the signal needs to arrive that much earlier than the clock edge at the destination.

+ Phase Shift xxxx How should i interpret this phase shift?
phase shift means there is clock skew between the source and the destination registers, positive skew means the destination clock arrives later than the source clock. i.e. we add the skew to the period

+ CPPR Adjustment xxxx What is CPPR. Is this Clock reconvergence pessimism removal?
I think it stands for Common Path Pessimism Removal. You can look at this explanation (basically removes common clock tree elements from the calculations for clock skew)

- Uncertainty xxxx what is this uncertainity?
this is the clock uncertainty, i.e. the clock period jitter. It's subtracted because it can reduce the period when the edges of a clock are closer together.[/]

= Required Time xxxx
this is when the signal needs to be at the register if you want it to meet setup time.

- Arrival Time xxxx
this is when the signal will arrive at the register based on the path delay from the source to the destination

= Slack Time xxxx
say if your period was 10 ns but the setup+phase_shift+cppr+uncertianty ended up as -3 ns then the data is required in 7 ns (10-3). If the data path delay is only 2 ns then you'll have a +5 ns slack, i.e. it passes timing. If the data path delay was 10 ns then you would have a -3 ns (7-10) slack, i.e. fails timing.

Clock Rise Edge xxxx
+ Clock Network Latency (Prop) xxxx
= Beginpoint Arrival Time xxxxv
not entirely sure what this is supposed to be in this timing report.[//i]

- - - Updated - - -



How was hierarchy removed? If a flattened design is just a removal of the hierarchical boundaries to make everything flat then timing shouldn't change. If flattening is optimizing logic across the boundaries, you'll end up with different results.

As I don't know the ETS tool I have no idea.

 

[ads-ee]

Phase shift term uses addition because, if it's positive number the destination clock path is longer than the source clock's path and it's a negative number if the destination clock path is shorter than the source clock's path.

The CPPR should be explained by looking at the explanation in the link, but in summary it's just removing the common clock path to both source and destination.

End Arrival Time doesn't seem to be the clock path, just by the name of it. As it's out of context, I'm not sure in what part of the timing report you saw that.