Explain yo me tester operation theory for DFT concept

[hezhengrong]

problems on DFT

Hi

who can give me a clear specification on DFT concept: I know that when synthesis, you can let the tool to insert scan i.e make the FFs become number of scan chains, this will make the ATPG tool to implemente.

so my questionis, the ATPG will generate the pattern for the design, does this pattern will be used in tester? because I do not understand the tester operation theory.

many thanks and waiting for the reply.

Regards

 

[yesme@]

problems on DFT

ATPG will generate the test pattern for your design. This test data will be used by your tester in test process. Tester will give this pattern to your chip by input/output port with its clock.

 

[spauls]

Re: problems on DFT

There is a very good book in DFT,
Digital System Testing and Testable design by Abrahmvicci .
go through it ,

 

[anishrai]

Re: problems on DFT

check out for a pdf by the name atpg_gd.pdf.....might be useful

 

[soloktanjung]

Re: problems on DFT

There is a very good book in DFT,
Digital System Testing and Testable design by Abrahmvicci .

where can i have the ebook? i've tried to search on the ebook link but could not find.


regards,
hairo

 

[SevenHsu]

problems on DFT

The different tester need different test pattern format, so before you generated the test pattern for tester you must provide it's format;

 

[dr_dft]

problems on DFT

Go to the DFT links on **broken link removed**
Look under DFT courses, and you will find out many good handouts from different Testing classes offered at different Universities.
One of the best set of handouts, is suprisingly, from National Tsing-Hua University from Taiwan