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If I'm not mistaken, the specs. mean:
pch_18 -> p-type transistor model name (0.18um technology)
w=10u -> the transistor poly gate width (NOT transistor width)
l=2u -> the transistor poly gate length
fingers=4 -> the number of gate fingers
total=8 -> total length: fingers X l
In the picture, there are 2 fingers, with w of 0.45um & l of 2.3um giving total of 4.6um.
A small addition to what cop02ia already explained.
w in this case refers to the width per finger = 10u
"simM" -- refers to the no. of multipliers.
So, "total" = no.of. fingers X no. of multipliers = 4 X 2 = 8
So, the total width W (and not length "L") will be 10u X 8 = 80u
With fingers, you can have S/D sharing but you cannot do that with multipliers.
Hope it helps!
Nothing wrong with the picture.
I just wrote them according to the PDK that was used.
In THIS layout picture, the PDK used refers to the transistor poly gate width (NOT transistor width) & similarly with the length. It depends on who wrote the PDK (I have a PDK from a different foundry referring to transistor dimensions as well).
In layout designs, usually creating instances have specs. for fingers, their lengths (or transistor width) & the total length (or width, whichever). I thought 'total' was referring to 8um ( I've never seen any PDK referring to total = finger X m, yet, but you learn something new everyday ).
In schematic, multiplier m value is given but not in layout (I'm referring to Cadence tools btw - m is the default name for multiplier, if you check the .cdsenv example file given by Cadence in the installation directory).