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For my opinion, the links as given by KAK111 demonstrate that some information that can be found in the internet have to be treated with care (some are really "garbage").
In the documents I cannot find any argument how to distinguish between slew rate and rise time.Or did I overlook some hidden information?
For example, as far as analog amplifiers (opamps) are concerned, the definition and measurement of the slew rate is applicable for circuits with feedback only.
More than that, it requires large signal operation with the consequence that the rising edge of the input signal overdrives/saturates the first stage until the feedback action brings this stage back to normal (linear) operation.
The small signal risetime is applicable for small signals only that do not cause the effect as described above.
Rise Time:
Amount of time it takes the output voltage to go from 10% of the Logic "1" level to 90% of the Logic "1" level. Measured in nS. Fall Time:
The time required for the output voltage to go from 90% of the Logic "1" level to 10% of the Logic "1" level. Measured in nS.
**broken link removed**
Slew is the transition time for signal. Transition time for input signal is called input slew and for output signal it is called output slew.
As far as I'm aware of, transition time is sometimes used as a collective term for both rise- and falltime, but has no specific meaning besides them. If rise- and falltime are applied to digital signals, they don't exactly mean small signal.
The important point is however to distinguish betweeen small signal rise- and falltime and large signal slewing time (respectively slew rate) of an amplifier, as mentioned in post #3.
In high speed OP data sheets, you sometimes find rise- and falltime specified for large signal, which is strictly spoken a combination of small signal circuit speed and slew rate. This corresponds to the fact, that these quanties can be measured e.g with an oscilloscope, that doesn't care about small or large signal.
According to my understanding this link cannot answer the original question, which - for my opinion - is related to analog operating circuits only.
And - more than that - it has nothing to do with the slew rate.
The question is placed in a digital forum. I agree, that slew rate isn't a usual term in digital circuit analysis. Nevertheless, digital output stages are involving analog effects, even a slew rate, that is created by transistor saturation currents and load capacitance. Also miller capacitance is present to some extent. To complete the confusion, some programmable logic devices are equipped ´with a "slow slew rate" option.
Without suggesting further detail discussions, just an example how the term slew rate is used in an Altera Cyclone III FPGA hardware handbook. The link to slew rate in analog circuits is in fact the assumption of a constant current driving the pin, similar to the slew rate achieved e.g. with an OTA. Although there are no current sources involved, the output transistors are operating in saturation for a larger part of the transition.
For ramp rates faster than 10 ns on I/O pins, |IIOPIN| is obtained with the equation
I = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate.
I think this is the right section to place this question. Slew, rise time and fall are very commonly used in ASIC physical design. Cell (AND, NAND etc) delay is calculated using input slew and output load. ASIC-SoC-VLSI Design: Delays in ASIC Design
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