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I simulated NMOS characteristic and attached image is the results.
From the graph, looks like saturation happen after green line.
Theoretically, saturation shall happen when Vds>Vgs-vth (red line)
Yes. The transistor enters saturation only at red line points but the region between green and red lines is also considered as Active region or Triode Region of the transistor's operation.
All the best.
I agree with sunny too.
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Yes. Its no load condition only. U got to see its model properties for further details on the transistor's behaviour.
Yes. The transistor enters saturation only at red line points but the region between green and red lines is also considered as Active region or Triode Region of the transistor's operation.
All the best.
I agree with sunny too.
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Yes. Its no load condition only. U got to see its model properties for further details on the transistor's behaviour.
Actually ideal curves as per Vds>Vgs-Vth for saturation will be different from the one which u got.
They will keep increasing till the red line points and will become constant from there on.
Here they seem constant from green line points itself. Its because of varying model properties. A transistor in any model will be defined by some 90 plus properties.
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The region between green line points and red line points is termed as "sub-threshold" region of operation.
It occurs just before entering the saturation region. This concept will be available in many VLSI text books.
Test bench shown in #3 is not correctly simulated as Drain-Source voltage is not varying with Drain-source resistance. I mean is by this circuit you will see false region shown by red line. MOSFET comes in saturation from green line, because slope is very less shows device reached saturation.
To correct test-bench, add 10k resistance at the drain and then simulate.
Test bench shown in #3 is not correctly simulated as Drain-Source voltage is not varying with Drain-source resistance. I mean is by this circuit you will see false region shown by red line. MOSFET comes in saturation from green line, because slope is very less shows device reached saturation.
To correct test-bench, add 10k resistance at the drain and then simulate.
Could you explain more detail?
Why we need to put resistor? Voltage of ideal voltage source won't change and we want to make Vds vary with Id current?
Drain-Source resistance = Ron?
I have tried with 100ohm resistor (10K is causes big voltage drop across resistor and Vds is too small)
can't really see big different from my simulation without resistor.
green line is estimated because neeed to consider voltage drop across resistorfor Vds
First thing you need to know that, before going to test the behavior of device, the device should have been correctly biased.
So now, please make sure, device can carry the biased drain current. If you sweep the supply, MOSFET should not cross break down limits.
Now, please tell us, what is the drain current, what is the device width, and what is the drain-source resistance?
(to limit drain current use the appropriate load resistance)
Reason is, if you bias incorrectly, may be the device model you are using not correct.
Hope you understood my point.
First thing you need to know that, before going to test the behavior of device, the device should have been correctly biased.
So now, please make sure, device can carry the biased drain current. If you sweep the supply, MOSFET should not cross break down limits.
Now, please tell us, what is the drain current, what is the device width, and what is the drain-source resistance?
(to limit drain current use the appropriate load resistance)
Reason is, if you bias incorrectly, may be the device model you are using not correct.
Hope you understood my point.
This nmos is 5V mos.
When both vds and vgs = 5V
Drain current is 5.6mA
width = 10um, length = 620nm,
drain source resistance for this condition = Vds/Ids = 791ohm....
I think MOSFET should not cross break down limit (vds around 7++ V) and working fine.
I feel that NMOS is biased in correct way. Please correct me if I am wrong.
Not really understand why trode and saturation region barrier different with ideal case.
Ah, better you bias it with 10-100uA. and then check the response.
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by the way, the shown MOSFET is 5V device, right? then it can't withstand 7V. Check the pdk please.
Ah, better you bias it with 10-100uA. and then check the response.
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by the way, the shown MOSFET is 5V device, right? then it can't withstand 7V. Check the pdk please.
Ya 5V device, but from the manual, mosfet will break down around 6.5V.
To bias nmos with 100u, I need very big drain resistor. I need to sweep input voltage to very large voltage (voltage drop across resistor is very big) so that vds is high enough for nmos to operate. It doesn't looks pratical for this testbench......
Actually ideal curves as per Vds>Vgs-Vth for saturation will be different from the one which u got.
They will keep increasing till the red line points and will become constant from there on.
Here they seem constant from green line points itself. Its because of varying model properties. A transistor in any model will be defined by some 90 plus properties.
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The region between green line points and red line points is termed as "sub-threshold" region of operation.
It occurs just before entering the saturation region. This concept will be available in many VLSI text books.
Thanks for your information but sub-threshold is the region where Vgs < Vth but still conduct a little bit. So, that region is not sub-threshold region.
What is meant by this?
For the transistor size you used, 10um width, it can't handle more than hundreds of uA. So thats how the MOSFET works.
It should make the VDS zero.
Or if you want to fetch current of 1-10mA, Use MOSFET size of 10umX1000. and then try.
Beta [uA/v^2] of the this nmos process > 2500 uA/V^2
and K > 0.55V^1/2
Id can goes up to 5mA when Vd = Vg = 5V for the size that selected.
What I can say on my simulation results now is green line is ideal and red line is non-ideal characteristic in my first post....
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Dear all,
Thanks for the idea.
I tried using lower VG and VDS value and the I-V curve is very close to idea case where saturation happen when Vds > Vg -Vth.
I can make conclusion that "velocity Saturation" and "mobility degradation" happen when Vgs too high causes carriers to scatter against surface and reduce carrier mobility.
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