exp
Full Member level 1
Hi,
Can anyone give me numbers from their experience of which linearity a plain diff pair in a modern process should be able to achieve?
Using a 28nm SOI process I built a simple diff pair with ideal current source loads and tail source (i.e., the output voltage is given by gm/gds). I am using pss and paq to measure IIP3 which is about -20dBm!!! (does not change significantly with different W and currents). This sounds suuuuuper low to me, I was hoping more for +20dBm ...
Thanks!
Can anyone give me numbers from their experience of which linearity a plain diff pair in a modern process should be able to achieve?
Using a 28nm SOI process I built a simple diff pair with ideal current source loads and tail source (i.e., the output voltage is given by gm/gds). I am using pss and paq to measure IIP3 which is about -20dBm!!! (does not change significantly with different W and currents). This sounds suuuuuper low to me, I was hoping more for +20dBm ...
Thanks!