example of using blocking assignment in verilog

[yuenkit]

Hi,

i normally use non-blocking assignment in my design and use blocking assignment in my testbench.

I wonder, under what situation do we use blocking assignment in design (to be synthesized)? Can you give example to illustrate your point? thank you!

 

[stevepre]

Rule of thumb:
non-blocking: used in sequential circuit
blocking: used in combinatorial circuit

It doesn't matter if it's testbench or synthesizable RTL code. Just follow this rule.

 

[yuenkit]

thnx,

But even in a sequential block, the circuit is basically combo logic + flipflop, so it's hard to separate out sequential logic and combo logic.

can some one shows me the code snippet of using blocking assignment (for synthesis purpose, not for testbench)?

even in fsm coding, i've come across some examples which are completely written using non-blocking. Although myself prefer using non-blocking assignment.

 

[shiv_emf]

that THUMB rules goes well !! is there any other possiblity for using blocking statements in squential design