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Synthesis Evaluation is a very important and difficult task. Your evaluation report will help in the decision of purchasing a very expensive tool.
The 1st step is to decide what design will you be using to evaluate both tools. It should be something that represents well your company's products but it should not be a huge design. Since you will need to perform several runs, a big design would be a productivity killer.
Use the same constraints for both tools in SDC format.
You should not trust the timing reports, the best would be set up a STA script in PT for the netlists you have synthesized. So you have a neutral timing engine judging the timing of your netlists.
If your company is fabless, be sure to use different libraries from all the FABs you are producing now or plan to produce in the future (i.e. UMC, TSCM, Dongbu, SMIC etc). If your current design is TSMC 0.18 and say your next design will be UMC 0.13 make sure you run the scripts with all these libs. From my experience tools deliver diferent results for different libs. Maybe DC is better with UMC 0.18 and worse for TSMC 0.13.
DC is more widely used, but RC is also a very good choice. And Cadence has release its first signoff quality timing tool ETS recently, which will become a strong competitor of Synopsys's PrimeTime. the de facto golden STA signoff tool.
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