Ethernet frame structure

[shaiko]

Every Ethernet frame begins with a preamble and followed by an SFD.
These serve both for synchronization and for indication that a new frame has started.

Now,
Suppose the payload of Ethernet frame accidently matches the bit pattern of the preamble+SFD.

What will stop the RX side from thinking that another transmittion just began?
Is there a mechanism that prevents such thing from happening?

 

[ads-ee]

If the PHY thinks a bit sequence in the payload is a preamble following an IPG then it will send everything it sees after that to the MMI/GMII/RGMII interface. It's up to the Layer 2 to figure out that the source destination and the Ethernet frame is bad.

I'm pretty sure a PHY syncs to the preamble following an IPG and forwards everything until the next IPG. I might be recalling incorrectly, but I think the IPG is encoded with IDLEs or such and won't occur in any payload. At least that has been my experience working with PHY chips and FPGA MACs.

You could read 802.3, which is currently freely available from the .