Ethernet connection of Spartan 3AN board

[ashwinidharpale]

My project name is Ethernet based announcement system using FPGA

I m using Spartan 3an 700 board.I am sending audio data from PC to FPGA board through rj45 connector. Then convert digital signal into analog form by using dac 2624 which is present on the fpga board.For sending data from PC to FPGA board I am using Borland Delphi 7 software.



I have problem in receiving data to FPGA by rj45 cabel.
1)how to know that the rj45 cable is connected or not and if any IP address is assigning to FPGA board.?
2)how to check rj45 connector?

 

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My project name is Ethernet based announcement system using FPGA

I m using Spartan 3an 700 board.I am sending audio data from PC to FPGA board through rj45 connector. Then convert digital signal into analog form by using dac 2624 which is present on the fpga board.For sending data from PC to FPGA board I am using Borland Delphi 7 software.

I have problem in receiving data to FPGA by rj45 cabel.
1)how to know that the rj45 cable is connected or not and if any IP address is assigning to FPGA board.?
2)how to check rj45 connector?

As you haven't said so, did you include the Etherenet MAC in the FPGA design? The board may have a Ethernet PHY chip connected to the RJ45, but that isn't going to give you an Ethernet connection without having the other OSI layers. How are you handing the TCP/IP protocol stack (are you using a microblaze?) or are you using UDP? Did you use a crossover cable? If you don't have one then plug the PC and the FPGA board into a switch/router.

The Ethernet MAC IP should have a signal on the user side that signals that a Ethernet cable is connected and there is a signal on it. The IP address (in layer 3) should be setup on the user side logic in the FPGA as it's not part of the MAC (layer 2). Use a address within a range like 192.168.xxx.xxx or 10.xxx.xxx.xxx as those are designated as private networks.

Mostly I'm just throwing things out there, as you never specified exactly what you've done so far or what your design looks like on more detailed level.

 

[ashwinidharpale]

The Sender Module was implemented in Borland Delphi 7 using the Wave Audio
Package for Delphi 7.0 specifically the Live Audio Recorder. This component records audio from a specified wave audio input device, and gives it to the application as data buffers. Using
Live Audio Recorder, the audio format and its sampling rate can be specified including the
length of the buffer in which the audio signal will be stored. For the packetization of the
audio signals, User Datagram Protocol (UDP) was chosen considering the fact that audio
data is to be transmitted in real time. UDP supports broadcasting which
is the primary goal of this project. The PC Sender Module is coded in Delphi using the
Borland Delphi 7 compiler.



When the Start button activates it record the sample and stores it in the buffer. The recorder is configured to sample Mono8 bit PCM at 48 KHz, while the size is predetermined to be
Filled at 4 ms of recorded voice. The bandwidth of the Mono8bit48kHz format is 384
kbps, i.e.48000 sec samples x 8bits sample = 384kbps. The Live Audio Recorder records
wave audio in user-defined buffers that include properties such as Buffer Count and
Buffer Length key. The Buffer Count of the Sender Module was set to 5 while the total
duration or buffer length was set to 20 ms. About 4 ms of single data buffer of the
discrete audio signal is framed to packets for transmission.






METHODOLOGY


Figure 4.1.system overview:

Figure 4.1 above illustrates the set-up of the Ethernet-based Announcement System. Audio signals from the microphone is fed into and processed by the personal computer (PC). Processing involves analog-to-digital conversion i.e. linear PCM coding of the analog audio and packetization or encapsulation of the audio data. The voice packets are then sent out through the Network Interface Card of the PC to the Local Area Network (LAN). Over the Ethernet, the audio packets are sent through the router to the FPGA receiver connected to the LAN through its onboard RJ45 connector. The FPGA board then performs de-packetization and conversion of the voice packets back to analog signals using its onboard digital-to-analog converter (DAC). Finally, the output analog signal is amplified and used to drive the speakers.


4.1 BLOCK DIAGRAM












Fig 4.2: block diagram

Audio signals from the microphone is fed into and processed by the personal computer (PC). Processing involves analog-to-digital conversion i.e. linear PCM coding of the analog audio and packetization or encapsulation of the audio data. The voice packets are then sent out through the Network Interface Card of the PC to the Local Area Network (LAN). Over the Ethernet, the audio packets are sent through the router to the FPGA receiver connected to the LAN through its onboard RJ45 connector. The FPGA board then performs de-packetization and conversion of the voice packets back to analog signals using its onboard digital-to-analog converter (DAC). Finally, the output analog signal is amplified and used to drive the speakers.



Procedure for Setting-up the System


The PC Server, Ethernet switch and FPGA are all connected by the twisted pair
Category 5 cable while the microphone, amplifiers and speakers are hardwired. The
Ethernet switch looks for the receiver and transmits the packets sent by the broadcaster.
The user initializes the Sender Module (broadcaster) on the PC server. When the Receiver
Module is switched on, the user can begin transmission by clicking the Start button on the
Sender Module dialog box and speaking through the microphone. The voice data is then
transmitted to the Receiver Module and heard through the audio speakers in real time

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So my question is how to know that RJ45 cable is connected or not to FPGA board.I am not getting any input from rj45 cable to FPGA.any other setting for transmitter.

 

[vGoodtimes]

You should look for reference ethernet designs for your board. While ethernet isn't that difficult, there are a lot of small details that can be hard to debug. Because the ethernet PHY is not on the FPGA, you also have to deal with interfacing to an external device.

For your immediate problem, my guess would be that you either have RESETn set to 0, or COMA set to 1, or do not have a clock provided to the external PHY. COMA is the powerdown mode. Once these are set up, and the PHY gets a clock, you should be able to see the link lights on the switch turn on. From there you would need to implement an ethernet MAC and any packet handling functions on the FPGA. A reference design can really help out here!

 

[raiatea]

In the schematic of the Spartan 3AN, the nRST pin of the SMSC LAN 8700PHY is strapped to a pull-down resistor.
The mode is boot-strapped with external pull-down to 10Base-T Half Duplex, auto-negociation disabled.

I would set the mode All Capable, enable the HP Auto-MDIX (for detection of direct connect LAN or cross-over patch cable), reset the PHY, then check the LINK led.

Let us know if that works!