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It is indeed a very common practice to fill every empty spot on the chip with Vdd-Vss capacitance to ensure a stable Vdd-Vss voltage.
Because the LV-NMOS gate-capacitance has a high capacitance/area ratio this device is also used a lot for this purpose. The problem is that this gate oxide is very sensitive and will fail easily during ESD stress. Voltage levels above 4V (even for short duration in order of ns) can damage the oxide and create a failure in the chip.
This means that when decoupling capacitance is created using this LV oxide device a very efficient power clamp is required to clamp the voltage below the dangerous levels. The good news is that the trigger speed for this clamp is not so important as for local protection of thin gate input buffers because of the added Vdd-Vss capacitance slows down the speed of voltage rise.
and to add on to ESDSolutions' comments, whether the MOS cap is at risk of ESD stress is also heavily relying on your ESD protection scheme and quality. usually high ESD current should have designated path, around the IOs, and all internal voltage rise shoudl be controlled well below the safe tolerate voltage for high performance mos devices. so if your ESD network is robust, then your mos caps should be safe.
Actually for most technology nodes multiple approaches exist. The most optimal solution further depends on the ESD requirements, constraints such as area, capacitance.
The mainly used approaches are
- RC triggered 'bigFET': a large NMOS/PMOS device reveives a gate/bulk bias during an ESD event. The current is shunted in active mode. Most of these can be simulated through SPICE as the normal device behaviour is used. You should certainly look into the influence of additional Vdd-Vss capacitance (original question in this post) on the dynamic trigger sensitivity.
Check references from the people at Freescale on the various EOS/ESD symposia. Good reading are a 2001 paper "Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies" and a 2003 paper "Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies".
Many other companies have introduced similar protection schemes (Intel, IBM, TSMC, National Semiconductor, ...)
- Snapback MOS device: a NMOS/PMOS device is triggered into so-called 'snapback' operation where the internal parastic PNP/NPN device is shunting the ESD current from drain (Collector) to source (Emiter). Certainly for advanced technology such as 65nm or 40nm the triggering voltage will need to be reduced through gate or bulk bias techniques because the avalanche breakdown voltage of the drain-substrate junction is close to or higher than the transient oxide breakdown voltage.
- SCR based approaches: A Silicon Controlled Rectifier is a device with intercoupled NPN/PNP bipolar transistors that turns into a PiN diode once triggered into high injection. These devices can be extremely area efficient but have led to many problems in the past such as latch-up, slow triggering, extensive process tuning required. Most if not all of these problems can be dealt with with the right triggering schemes and layout experience. Look into the following references:
2001 paper "GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes", a 2002 paper "High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC
Operation" and a 2008 paper "A Dual-Base Triggered SCR With Very Low Leakage Current And Adjustable Trigger Voltage", all published at the EOS/ESD symposia.
I must add that in all cases a lot of companies have spent time and money in creating and optimizing these clamps. To safeguard this effort companies are typically using patents. This means that you can not copy the solutions as-is without a license agreement.