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ESD Protection Question

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taoly

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In many COMS circuits, the ESD protection circuits are offen constructed with large NMOS or PMOS. I want to know what is the relationship between the ESD robustness and the sizes of these MOS transistors. Is there any papers or documents about this question? Or any simulation method?

Thanks!
 

As a rule the bigger the sizes are, the better ESD is. The ESD size rule is normal 30um to 60um. If your size is big, the figure must be many. The current flows better.
 

watersky,

I think the bigger the size, the better the ESD may not be true as it is not like current. ESD depends on layout and you will see multi-fiinger structure may saturate in ESD robustness even you increase further the finger size as ESD heats up in the middle of the finger instead of all fingers turn on. That's the real fact in silicon.

taoly,
You should check for NMOS IT2 (second breakdown current) and it is a mA/um. This number tells you how much 1um increase can lead to how many mA can have for NMOS ESD robustness in snapback mode during ESD zapping. This number you can only ask foundry to provide to you.

For example, IT2=13mA/um, then for a HBM2kV zapping, its peak is around 1.3A=1300mA, so you can simply calculate 1300(mA/um)/13mA=100um, so it means 100um NMOS can withstand HBM2kV ESD, if all 100um can be turned on at the same time, take some margin, of 20%, you may draw 120um, with 4 fingers with each @30um.
However, this is JUST a typical NMOS operable in snapback, and most ppl will do active trigger to have early snapback to prevent large power=VI heats up the fingers before it snapbacks really, by gate driven or substrate trigger.

PMOS can be of similar size as NMOS
 

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