ESD Layout Design Rule Checker

[DoctorProf]

I want to implement an Automatic ESD DRC checker for our analog designs. I've found several papers and have talked to many companies. There currently is not a commercial ESD Rule Based Design checker. Many of the larger companies have implement some form of ESD checker. These can range from simple checker that look for peak current and check the layout for electromigration/fusing rules to running simulations of the ESD protection and comparing the voltages to what devices can survive.

Does anyone have examples of ESD rule checker that are used in their company.

Thanks,

Dr.Prof