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ESD HBM model Test Bench

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dkace

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esd hbm

Hi!

I am trying to set up the correct test bench for ESD HBM in an on-chip PAD.

My approach is to create the correct ESD HBM and then to build a rail-to-rail ESD protection circuit attached to the PAD.

I want to verify my thinking, so I would appreciate any suggestions or guidance on doing the above steps.

Thanks,

D.
 

dick_freebird

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hbm model

Make yourself a "stinger" macromodel with a vpulse, 1.5K resistor, 100pF
capacitor in series pin-pin. Vpulse risetime to be pretty short, pulse level
is your ESD voltage. The DUT completes the current loop. You can place
the macro as you see fit. If you propertize the macro you can attach many
and activate one, to "shotgun" the part in one parametric analysis loop. A
pin-pin vcvs so you can view difference, rather than absolute pin voltages,
is helpful for plots you want to criticize against ratings.

In general you're better off thinking about the current loop, than voltages,
when you design for ESD. The current -will- make the round trip and you
are looking primarily to return it to the source as losslessly, and at as low a
voltage as possible (kind of the same thing, but not entirely).

Diode-rail_clamp-diode schemes are common but not necessarily the
ideal. As an analog guy I prefer star arrangements, but this needs a lot
more total clamp area, using only a fragment for any given pin-pair. A
more uniform (like digital) part favors the former.
 

dkace

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esd hbm tester

Thanks for the reply.

This is what I also found and tested but I am not sure if is the correct one. Do you have any reference or a test bench I can verify my set up?

D.
 

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