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ESD Current path flow on this Diagram

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I was reading about ESD diode arrays and protection devices and saw the below diagram.

My question is:

In this diagram below, can someone help me to draw/identify the path of current flow through the ESD diode (RClamp part) when an ESD strike occurs?

enter image description here

Also, I saw the datasheet of the Rclamp part over here.

enter image description here

I think that the arrangement of the diodes of the Rclamp part is different from the first one and the one in the datasheet. Can someone clarify which one is better?

Also, I would be grateful if the current path for the datasheet part is also helped with. Thank you.
 

Hi,

upper picture is useless.

lower picture:
* overvoltage on PIN1 --> upper right diode --> zener --> GND
* undervoltage on PIN1 --> upper left diode --> GND
... and so on

Current flows in a loop, thus even the lower picture misses the "external loop"

Klaus
 
My best understanding is this.
ESD may be either polarity and applied to any wire(s). The magnetics terminate with 75 ohm differential via cap. There is a CM choke to attenuate with some CMRR. This combo of differential and common mode will attenuate the slew rate and amplitude of the arc. Each pair is rectified thru a full-wave diode bridge (FWDB) then clamped by the Zener which is shared by
Rx and Tx pairs.

The arc current may travel in any forward biased path depending on polarity and travel between stray capacitance on pairs, magnetics and stray inductance on traces. This is why grouping close and on same side as the magnetics is given.

- the Rclamp (FWDB) seems to clamp more paths and polarities.
 

Besides the question where the current loop is, first diagram misses the essential RClamp ground connection.
 

Hi,

upper picture is useless.

lower picture:
* overvoltage on PIN1 --> upper right diode --> zener --> GND
* undervoltage on PIN1 --> upper left diode --> GND
... and so on

Current flows in a loop, thus even the lower picture misses the "external loop"

Klaus
Thank you very much for the answer.

So, when the PIN1 has undervoltage, the device won't clamp the undervoltage to a specific value since the ESD voltage doesn't pass through the zener, right? Which would imply that the device doesn't work or clamp undervoltages, right?
 

Negative transient is clamped directly to ground (center tab connection), as explained by KlausST.

By the way, did you notice the forum rule to post similar questions in one thread?
 
Negative transient is clamped directly to ground (center tab connection), as explained by KlausST.

By the way, did you notice the forum rule to post similar questions in one thread?
Oh, so the negative transient is clamped to 0V, is it? Sorry, it is not clear.

Oh, I didn't notice te rule. I will follow it from now on.
 

You see the diode circuit, how can it be unclear if it clamps negative voltage?

ESD currents are in an order of several 10 A, the pulse clamp voltage is surely > 0 V (or 0.7 V diode forward) but lower than positive clamp voltage of zener + diode.
 

The current loop can be "any to any, and back again". The specific
clampage asked about can protect both pins to GND or, via the
up-diode and zener, to each other (via GND, with drops) or to the
zener limit voltage (> max VDD, but no higher than needed as this
goes to ESD clamp effectiveness vs internal weak points).

Pin voltage range not-clamping will be GND-Vf (likely 0.7V nom)'
up to (Vz+Vf) and the Vz is probably binned for various normal
VDDs. But likely too, this style loses steam below 3.3V-reliable
gate oxides with all the series drops.
 

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