ESD and Latch Up protected Layout

[krrao]

Hi All,
If I have a inverter connected directly my pad, then how do I layout this inverter protecting from ESD and Latch Up issues ? please explain in details.

consider for example W/L of PMOS = 200/0.5 amd W/L of NMOS = 75/0.5.
--
warm regards,
krrao.

 

[prcken]

according to the size of the inverter you give, i assume this is an output inverter buffer, it is the drain connect to the pad. so the drain is ESD sensitive node.
there are two methods to prevent ESD.
1. layout the PMOS and NMOS device as ESD device (use SAB layer at the drain side), and you should add more explicit ggnmos and gdpmos ESD devices to meet the total ESD area requirement according to design rule check.
2. or you can simply add current limiting resistors between pad and output of the inverter with explicit ESD devices.
in the second way, you dont have to layout the inverter devices as ESD device so that silicon area is saved.

for LU issue, just add double guardring. dont put PMOS and NMOS too close, DRC can help you to check it.

 

[krrao]

according to the size of the inverter you give, i assume this is an output inverter buffer, it is the drain connect to the pad. so the drain is ESD sensitive node.
there are two methods to prevent ESD.
1. layout the PMOS and NMOS device as ESD device (use SAB layer at the drain side), and you should add more explicit ggnmos and gdpmos ESD devices to meet the total ESD area requirement according to design rule check.
2. or you can simply add current limiting resistors between pad and output of the inverter with explicit ESD devices.
in the second way, you dont have to layout the inverter devices as ESD device so that silicon area is saved.

for LU issue, just add double guardring. dont put PMOS and NMOS too close, DRC can help you to check it.

Hi prcken,

You said layout the PMOS & NMOS as ESD devices. I am new to ESD layouts, will you please explain the 1st method elobarately.

--
warm regards,
krrao.

 

[prcken]

do you have ESD design rule provided by the foundry?
that document explains how to draw these MOS based ESD devices with minimum dimensions required according to the process you are using.