Errors in Verilog code with for loops

[fakeha_s]

for loop

I am pasting part of my verilog code i converted the for loops if-else statements but the simulation were not as required ,i am making some mistake which i am unable to understand

code using for loop
for(a=63;a>=16;a=a-1)
begin //message4[a=63]inverted
//takes one bit of message4 converts it if check1 notequal to zero converts the bit
//to its original value and now inverts the next neighbouring bit a=62 and uses it in
//the nested for loop
message4[a]=~message4[a];
for(b=63;b>=0;b=b-1)
begin //this loop runs 63 times using the message4[a]
r2[16]=r2[15];
r2[15]=r2[14];
r2[14]=r2[13];
r2[13]=r2[12];
r2[12]=(r2[16]^r2[11]);
r2[11]=r2[10];
r2[10]=r2[9];
r2[9]=r2[8];
r2[8]=r2[7];
r2[7]=r2[6];
r2[6]=r2[5];
r2[5]=(r2[16]^r2[4]);
r2[4]=r2[3];
r2[3]=r2[2];
r2[2]=r2[1];
r2[1]=r2[0];
r2[0]=(message4 ^ r2[16]);

end



message4[a]=~message4[a];
cal_crc_code0=r2[16:1];
check1=cal_crc_code0^frame_crc_code;
r2=17'b0;
b=63;

if(check1==16'b0)
begin
error_bit=a;
message4[a]=~message4[a];
correctmessage=message4[63:16];
again=1;
end
//again is used further in code and makes
//a= 16 so that if at any point check1=0 the outer loop stops and no further
//calculation occurs if at any point
//check1 is not equal to zero outer loop continues from 63 to 16


end


code using if-else statements

if(a>=16)
begin
if(h==0)
message4[a]=~message4[a];
if(b>=0)
begin
h=1;
r2[16]=r2[15];
r2[15]=r2[14];
r2[14]=r2[13];
r2[13]=r2[12];
r2[12]=(r2[16]^r2[11]);
r2[11]=r2[10];
r2[10]=r2[9];
r2[9]=r2[8];
r2[8]=r2[7];
r2[7]=r2[6];
r2[6]=r2[5];
r2[5]=(r2[16]^r2[4]);
r2[4]=r2[3];
r2[3]=r2[2];
r2[2]=r2[1];
r2[1]=r2[0];
r2[0]=(message4 ^ r2[16]);
b=b-1;
if(b==-1)
begin

cal_crc_code0=r2[16:1];
check1=cal_crc_code0^frame_crc_code;
r2=17'b0;
b=63;

if(check1==16'b0)
begin
error_bit=a;

correctmessage=message4[63:16];
again=1;
b=0;
h=1;
end
else if(check1!=16'b0)
begin
message4[a]=~message4[a];
a=a-1;
h=0; //if check1 not equal to zero next message4 bit should be inverted


end
end

end
end

 

[echo47]

for loop

Someone can probably help you much better if you show a complete module that we can compile, and then briefly explain its general function.

Also please use the "code" button. That makes indented source code much easier to read.

 

[fakeha_s]

Re: for loop

sending the code and test bench file please check the code ,synthesize and see if the result matches the attched jepeg file,i am using ISE 6.2 PROJECT NAVIGATOR

 

[echo47]

for loop

Please explain your difficulty. Why can't you synthesize and compare?

I don't see any jpeg file. I see untitled.bmp - a ModelSim output. It looks like a behavioral simulation, before place-and-route. Is it suppose to be a good result, or bad result, or what?

Your design has too many I/O for xc3s200-4-ft256.

Your clocked logic if full of = blocking assignments. That could cause big trouble. You should use <= non-blocking assignments.

Not clear what your code is suppose to do. Something about error checking.

Please don't upload any more large ISE intermediate files.

 

[fakeha_s]

Re: for loop

with for loops the code is running perfect and the bitmap file is the saved modelsim simulation result but when i tried to synthesize the file the synthesizer would not synthesize (it keeps on thinking)so i replaced the for loop with if-else statements now i am not getting the required results ,i am not using the if-else statements correctly if you can just look at the if-else statements replacing for loops and determine what is the error they should function as the for loops were (you can see my earlier mail in which i mailed both the code for for loop and if-else statements)
please i want my code to run as soon as possible i have to submit it
the code receives a 64 bit frame it first checks whether all 64 bits have been received(this portion is running fine) now it checks whether there is any error (this is also working fine)if there is any error it checks which type of error one bit ,two consecutive bits,or burst of error,or maybe in bits which are apart from each other and then determines the exact bit position(this portion is not running correctly)
(it showed correct simulation with for loops but i was not able to synthesize,i received error low virtual memory and somebody told me you donot use for loops you design your code in terms of hardware or use if-else statements)