Errors after running DRC for digital ICs

[aifi]

hi..

i got problem when i run drc after importing gdsii file to virtuoso, it's not clean, i realized that the errors were coming from the standard cells itself..why? is it different drc file for digital design compare to analog design? please help me....

thanks

 

[shilong_xu]

Re: drc for digital ic

as i know, different process should have different DRC, because the rule is corresponding one process, such as analog and digital IC should have different DRC file

 

[aifi]

Re: drc for digital ic

oh really....but i feel confuse by the problem when i see the minimum space between met1 to met1 got error...it's also heppened to the other layer..

 

[cadenceguy]

Re: drc for digital ic

Std cells are designed for partictular process.
Is the error in the block itself or between overlapping blocks?
Ie Via_cell

Does your Manual & DRC deck have the same values ?

Usually the DRC is more comprehensive, but may generate false errors.

Make sure that you are using up to date decks.
Check your foundary for most up to date decks.

Have fun !