Errors about Spartan6 BUFIO2

[gongyuwei]

Hi, I am using Spartan6 FPGA to receive output data of AD. The outputs of AD contain a clock and 12 bit data lines. In FPGA, I connect BUFIO2 to input clock, and use this clock to sample 12 bit data. However, I must process this data. BUFIO2 is regional clock, and the processing of data should be in global clock. I insert a FIFO between the two clocks. Now I want to connect 12 bit data to data input of FIFO, but it seems BUFIO2 can not drive internal logic. ISE gives me errors too. If this is true, how do I transmit the 12 bit data between logics after FPGA samples these data? How do I use BUFIO2 correctly?

 

[axcdd]

What error do u get, because everythink should be working corretly if i place external clock to BUFIO2 on spartan 6

 

[permute]

BUFIO only drives IO logic.
BUFR can be connected to the bufio, and can drive a region.

 

[gongyuwei]

BUFIO only drives IO logic.
BUFR can be connected to the bufio, and can drive a region.

Can BUFR be used for spartan6?

 

[mrflibble]

Can BUFR be used for spartan6?

Njet. For the spartan-6 equivalent of that primitive, check out BUFIO2 and BUFCE. You can R all about it in TFM: https://www.xilinx.com/support/documentation/user_guides/ug381.pdf

 

[gongyuwei]

I searched BUFCE in ug381, but I can not found it. Now I know that BUFIO2 is used for high speed interface(>100MHz), in which case data always are transmitted in serial. Then SDR and DDR is needed, so high speed clock can be connected to the clock input of SDR and DDR through BUFIO2. After SDR and DDR, data are converted to parallel data, so BUFIO2 has a DIV output to generate a divided clock for parallel data. This DIV output can be connected to BUFG and drives the logic in FPGA. Then parallel data are processed under this global clock. However, is there some skew between this global clock and parallel data? How do FPGA remove this skew and align the two?