error while using formality tool

[anuradha.verma]

hello,

While loading the design(vhdl file) in formality tool following error appears

"RTL interpretation message where produced during read.
verification results may disagree with logic simulator"

how can i remove this error

 

[sam536]

you need to analyze this error is valid or not ?.
If any translation issues or you have plan to fix these errors in the next RTL relase and want to proceed for FV, use below command .

set hdlin_warn_on_mismatch_message "FMR_ELAB-X" ; X value can get from your log report Warnings, which shows above the FM-089 Error .
If you can share the log file, we can justify the warnings.

Usually, this will happen due to Pragmas . Pragmas can be switched off/on with hdlin_ignore_translate switch in Fv.
It may be FSM issue or serious issue regarding the design. Need to revisit your RTL code in the next RTL version.

These errors cant be ignored and should have waiver from Design team to prove Formality reports.

Note : Please provide the snapshot of error report next time to get appropriate answers for query.

Regards,
Sam

 

[anuradha.verma]

HI

Thanks ....i used the set hdlin_warn_on_mismatch_message "FMR_ELAB-X"...the error message changed to warning.and my file got loaded properly.
but while veriying the design it got failed.the failed report lists some signals ....how to solve that.

 

[sam536]

Now elaboration issues are resolved.
Next step is, how is matching report in formality. If you are satisfied with matching report , need to investigate the failing verification points. Did you

how to resolve failing points.

1. Did you use SVF ? .
2. How many points are failing?. Is it more than 50% , there will be Setup issue
3. Is there any pragma interpretation wrong?.
4. Parse through all the log errors and warnings and will get clue.

down load the first PDF from below location

https://solvnet.synopsys.com/retrie...advSearch&otSearchResultNumber=22&otPageNum=3

Let me know if you cant access the below link. solvnet account is required for this.

Regards,
sam

 

[anuradha.verma]

Now elaboration issues are resolved.
Next step is, how is matching report in formality. If you are satisfied with matching report , need to investigate the failing verification points. Did you

how to resolve failing points.

1. Did you use SVF ? .
2. How many points are failing?. Is it more than 50% , there will be Setup issue
3. Is there any pragma interpretation wrong?.
4. Parse through all the log errors and warnings and will get clue.

down load the first PDF from below location

https://solvnet.synopsys.com/retrie...advSearch&otSearchResultNumber=22&otPageNum=3

Let me know if you cant access the below link. solvnet account is required for this.

Regards,
sam

1) yes i used the svf file created by design compiler .
2) there are 20 signals in my design which are failing.

 

[sam536]

Is this failing points are undriven signals?. What is the % failure points?. Is all 20 signals are in bus or different signals.

Use the downloaded PDF to debug .

Best of luck.

Regard , Sam