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Error when synthesizing in ISE: design is too large to fit the device

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guzhal

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I am able to synthesize my design in ISE9.2i. When i try to implement,it is throwing an error

error:The design is too large to fit the device. (In packing phase)
how should i make my design to fit into the device
 

JPR75

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Re: help in ISE

Hi,

The easiest way is to choose a bigger FPGA or CPLD. Otherwise, you have to optimize your design.
Usually, it's a good idea to keep 20% to 40% of free space in your FPGA for future updates.
 

gck

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Re: help in ISE

I do agree with guzhal.

Try with higher Target device.
First see the device utilization, if it is more than 90% then such error may come. So try to optimize the design with giving Area as optimization goal. If doesn't work then need to change target device
 

ameed

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Re: help in ISE

hi,
you need to optimise or choose fpga of bigger size:idea:



thanx......
 

echo47

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help in ISE

How big is your design, and how big is your device?

If it's an FPGA, check the "device utilization summary" or "design summary" to see how many resources (flip-flops, block RAMs, I/O's, etc) were used. Do the numbers seem reasonable for your design? If not, maybe something went wrong during synthesis, such as RAM implemented as thousands of flops. Also check the synthesis report for suspicious warning messages.

Maybe helpful, "Area Reduction Strategies":
https://toolbox.xilinx.com/docsan/xilinx9/help/iseguide/html/ise_xst_area_reduction_strategies.htm
 

cheggy

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Re: help in ISE

If chip resources aren't spent, try with releasing IO pins (remove *.ucf file).
 

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