error was encountered while running xflow.

[jigna]

I am trying to design a simple 4th order fir filter using system generator with sampling frequency 10k and generating it on spartan3e xc3s500e4fg320 configuration board to perform hardware co-simulation..here is the schematic View attachment untitled.bmp
At the end of generation process an error was encountered showing 1 constraint not met while running xflow. the detailed report is attached here View attachment xflow.txt
Timing analysis report shows that all constraints were met. View attachment time.txt.
How to troubleshoot this problem????

 

[axcdd]

im not good at reading and debugging xilinx attachments but i see that IBUFG got constraint of 20ns (50HMz) while you use 10 kHz sampling frequency (?).

Anyway u can achive better timing results by taking care of longest data path .In this circuit it is mul and 4x sum for last coefficient, adding some pipeline registers to this tree of adders will help or just use transponse FIR circuit