ERROR:Pack:1654 - The timing-driven placement phase encountered an error

[venky.817]

i am getting this error while executing code in xilinx vlx6365t kit...

ERRORlace:1153 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk1> is placed at site <J19>. The corresponding BUFGCTRL
component <clk_inst> is placed at site <BUFGCTRL_X0Y1>. The clock IO can use
the fast path between the IOB and the Clock Buffer if a) the IOB is placed on
a Global Clock Capable IOB site that has the fastest dedicated path to all
BUFGCTRL sites, or b) the IOB is placed on a Local Clock Capable IOB site
that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP
or BOTTOM). You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "clk1" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.

 

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This occurs when you have a clock input that needs to traverse from one I/O bank into a second I/O bank to say reach a MMCM or in your case a BUFGCTRL. I recall for V6 this is allowed if using a MRCC clock input but not with an SRCC clock input.

Without knowing what pins/MMCM/BUFG you are using in your design I can't tell you specifically what is the problem.

If the crossing of the clock into another bank was intentional then either make sure the clock is on an MRCC clock pin and that the clock is restricted to the bank in comes in on and the adjacent banks above and below that bank. You can also set the CLOCK_DEDICATED_ROUTE to BACKBONE (I think that's the term). This will allow the clock to reach any MMCM or BUFG in the part, but the tools won't compensate for the insertion delays in this case.