Error on signal assignment using counter on FSM

[zorax85]

Using the following code lines, generates error (HDLParsers:808 - + can not have such operands in this context.).

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Prom_BPI_IF_FSM is
    Port ( RESET: in  STD_LOGIC;
              PROM_CE : out  STD_LOGIC;
           PROM_WE : out  STD_LOGIC;
              PROM_OE : out  STD_LOGIC;
           PROM_ADV : out  STD_LOGIC;
           PROM_WAIT : in  STD_LOGIC;
           PROM_DATA : inout  STD_LOGIC_VECTOR (15 downto 0);
           PROM_ADDR : out  STD_LOGIC_VECTOR (27 downto 0));
end Prom_BPI_IF_FSM;
 
 
 
architecture Behavioral of Prom_BPI_IF_FSM is
 
type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, DATA_READING_PLUS, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count: std_logic_vector(27 downto 0);
 
 
begin
 
    prom_bpi_if_p: process(current_prom_bpi_state)
 
    begin
 
        next_prom_bpi_state <= current_prom_bpi_state;
 
        case current_prom_bpi_state is
            when IDLE =>
                if (RESET = '0') then
                next_prom_bpi_state <= START_READ;
                end if;
            
            when START_READ =>
                count <= "0000000000000000000000000000";
                PROM_CE <= '0';
                PROM_ADV <= '0';
                PROM_OE <= '1';
                PROM_ADDR <= (others => '0');
                next_prom_bpi_state <= DATA_READING;
                
            when DATA_READING =>
                if  count < ("0000000000000000000000001111") then
                PROM_CE <= '0';
                PROM_ADV <= '0';
                PROM_OE <= '0';
                PROM_ADDR <= (count);
                next_prom_bpi_state <= DATA_READING_PLUS; else
                next_prom_bpi_state <= FINISH; 
                end if;
                
            when DATA_READING_PLUS =>
                count <= count + "0000000000000000000000000001";
                next_prom_bpi_state <= DATA_READING;
            
            when FINISH =>
                PROM_CE <= '1';
                PROM_ADV <= '1';
                PROM_OE <= '1';
                next_prom_bpi_state <= IDLE; 
        end case;
    end process;
end Behavioral;

---

I would like just addressing a Parallel Prom through a CPLD. Can someone help me?



Thanks!

 

[lucbra]

you will need a library to deal with the '+' operator

add IEEE.NUMERIC_STD.ALL and make count an unsigned.

BTW, in stead of writing

count <= "0000000000000000000000000000";

you could simply write

count <= (others => '0');

less typing, and regardless of the width of the signal allways valid.

 

[permute]

tip, also count <= (count'range => '0') . this comes up more in the "if count = (count'range => '1')".

also, its not a clocked process, so count <= count +1 won't synthesize. next_count <= count + 1 would be needed. a clocked process would also be needed to register next_state and next_count.

 

[zorax85]

lucbra

Re: Error on signal assignment using counter on FSM
you will need a library to deal with the '+' operator

add IEEE.NUMERIC_STD.ALL and make count an unsigned.

BTW, in stead of writing
Code:

count <= "0000000000000000000000000000";

you could simply write
Code:

count <= (others => '0');

less typing, and regardless of the width of the signal allways valid.

Thank for the suggestion, it seems works. I will do a testbench to know if it is ok for my purpose.

permute

Re: Error on signal assignment using counter on FSM
tip, also count <= (count'range => '0') . this comes up more in the "if count = (count'range => '1')".

also, its not a clocked process, so count <= count +1 won't synthesize. next_count <= count + 1 would be needed. a clocked process would also be needed to register next_state and next_count.

Ah, ok... I understood. But you mean that I should do as like you explained, or I can use however this "version" without clocked process, in order to addressing the prom?

 

[permute]

the combinatorial circuit "x = x +1" doesn't make any sense, as if x=1 then x=2 then x=3 then x= ... With no time between updates to x, the value of x is not known. You have chosen the two-process model for the state machine and logic. this would mean making a next_x, and then setting x <= next_x in the combinatorial process.

As for assigning a value of zero, (others => '0') is more common. I merely brought up (x'range => '0') as an alternative as it can be used as a condition in if-else statements.

in simulation, count is only updated when current state changes, so it appears to work. Synthesis ignores the sensitivity list, which is the only reason the circuit worked in simulation. if you add count to the sensitivity list, it will likely complain about the combinatorial loop, or fail to simulate.

using numeric std, you can also do x <= x + 1. this is useful as a literal "0001" might be ambiguous in some cases.

 

[zorax85]

the combinatorial circuit "x = x +1" doesn't make any sense, as if x=1 then x=2 then x=3 then x= ... With no time between updates to x, the value of x is not known. You have chosen the two-process model for the state machine and logic. this would mean making a next_x, and then setting x <= next_x in the combinatorial process.

As for assigning a value of zero, (others => '0') is more common. I merely brought up (x'range => '0') as an alternative as it can be used as a condition in if-else statements.

in simulation, count is only updated when current state changes, so it appears to work. Synthesis ignores the sensitivity list, which is the only reason the circuit worked in simulation. if you add count to the sensitivity list, it will likely complain about the combinatorial loop, or fail to simulate.

using numeric std, you can also do x <= x + 1. this is useful as a literal "0001" might be ambiguous in some cases.

Yes, it's true... I've been correct my code, adding the missing lines. However, I still have some problems. Because when the system go in DATA_READING state, instead of doing 15 time cycles operation, it seems block the iteration after the first step.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Prom_BPI_IF_FSM is
    Port ( 
    PROM_RESET               : in std_logic;
    PROM_CLK               : in std_logic;
    PROM_WAIT              : out std_logic;
    PROM_CE                : out std_logic;
    PROM_ADV               : out std_logic;
    PROM_OE                : out std_logic;
    PROM_WE                : out std_logic;
    PROM_ADDR              : out std_logic_vector(27 downto 0)
    --PROM_DATA              : in std_logic_vector(15 downto 0) -- remember to make inout
    );
end Prom_BPI_IF_FSM;
 
 
 
architecture rtl of Prom_BPI_IF_FSM is
 
type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count: unsigned(27 downto 0);
 
begin
 
 
    prom_bpi_if_c: process(current_prom_bpi_state, PROM_RESET)
 
    begin
        count <= (others => '0');
        PROM_WAIT   <= '0';
        PROM_CE     <= '0';
        PROM_ADV    <= '0';
        PROM_OE     <= '0';
        PROM_WE     <= '0';
        PROM_ADDR   <= (others => '0');
        
        
 
        case current_prom_bpi_state is
            when IDLE =>
                if (PROM_RESET = '0') then
                next_prom_bpi_state <= START_READ;  else next_prom_bpi_state <= IDLE;
                end if;
            
            when START_READ =>
                count <= (others => '0');
                PROM_WAIT   <= '0';
                PROM_CE     <= '0';
                PROM_ADV    <= '0';
                PROM_OE     <= '1';
                PROM_WE     <= '0';
                PROM_ADDR   <= (others => '0');
                next_prom_bpi_state <= DATA_READING;
                
            when DATA_READING =>
                if  (count < 15) then               
                PROM_WAIT   <= '1';
                PROM_CE     <= '1';
                PROM_ADV    <= '1';
                PROM_OE     <= '1';
                PROM_WE     <= '1';
                count <= count + 1;
                PROM_ADDR <= STD_LOGIC_VECTOR(count);
                next_prom_bpi_state <= DATA_READING; else next_prom_bpi_state <= FINISH; 
                end if;
 
                
                        
            when FINISH =>
                PROM_WAIT   <= '0';
                PROM_CE     <= '1';
                PROM_ADV    <= '0';
                PROM_OE     <= '1';
                PROM_WE     <= '0';
                PROM_ADDR   <= (others => '0');
                next_prom_bpi_state <= IDLE; 
        end case;
    end process prom_bpi_if_c;
    
    prom_bpi_if_r: process (PROM_CLK)
        
        begin
            if rising_edge(PROM_CLK) then
                current_prom_bpi_state <= next_prom_bpi_state; 
            end if;
    end process prom_bpi_if_r;
    
    
end architecture rtl;

---

 

[TrickyDicky]

again, same problem. You have count <= count + 1; inside the asynchronous portion. So it just gets to 15 instantly the state goes to DATA_READING. You need something like:

"next_count <= count + 1;" in the async process and then put "count <= next_count;" in the clocked process;

 

[zorax85]

again, same problem. You have count <= count + 1; inside the asynchronous portion. So it just gets to 15 instantly the state goes to DATA_READING. You need something like:

"next_count <= count + 1;" in the async process and then put "count <= next_count;" in the clocked process;

I made changes as you suggested, but nothing is changed

 

[lucbra]

what does your code look like now?

 

[zorax85]

HERE IS THE CODE

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Code Visual Fox Pro - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Prom_BPI_IF_FSM is
    Port ( 
    PROM_RESET               : in std_logic;
    PROM_CLK               : in std_logic;
    PROM_WAIT              : out std_logic;
    PROM_CE                : out std_logic;
    PROM_ADV               : out std_logic;
    PROM_OE                : out std_logic;
    PROM_WE                : out std_logic;
    PROM_ADDR              : out std_logic_vector(27 downto 0)
    --PROM_DATA              : in std_logic_vector(15 downto 0) -- remember to make inout
    );
end Prom_BPI_IF_FSM;
 
 
 
architecture rtl of Prom_BPI_IF_FSM is
 
type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count, next_count: unsigned(27 downto 0):= (others => '0');
begin
        
    prom_bpi_if_c: process(current_prom_bpi_state, PROM_RESET)
    
    begin
    
        PROM_WAIT   <= '0';
        PROM_CE     <= '0';
        PROM_ADV    <= '0';
        PROM_OE     <= '0';
        PROM_WE     <= '0';
        PROM_ADDR   <= (others => '0'); 
        
        
        case current_prom_bpi_state is
            when IDLE =>
                if (PROM_RESET = '0') then
                next_prom_bpi_state <= START_READ;  else next_prom_bpi_state <= IDLE;
                end if;
            
            when START_READ =>
                
                PROM_WAIT   <= '0';
                PROM_CE     <= '0';
                PROM_ADV    <= '0';
                PROM_OE     <= '1';
                PROM_WE     <= '0';
                PROM_ADDR   <= (others => '0');
                next_prom_bpi_state <= DATA_READING;
                
            when DATA_READING =>
                if  (count < 15) then               
                PROM_WAIT   <= '1';
                PROM_CE     <= '1';
                PROM_ADV    <= '1';
                PROM_OE     <= '1';
                PROM_WE     <= '1';
                PROM_ADDR <= STD_LOGIC_VECTOR(count);
                next_count <= count+1;
                next_prom_bpi_state <= DATA_READING; else next_prom_bpi_state <= FINISH; 
                end if;
            
            when FINISH =>
                PROM_WAIT   <= '0';
                PROM_CE     <= '1';
                PROM_ADV    <= '0';
                PROM_OE     <= '1';
                PROM_WE     <= '0';
                PROM_ADDR   <= (others => '0');
                next_prom_bpi_state <= IDLE; 
        end case;
        
    end process prom_bpi_if_c;
    
    prom_bpi_if_r: process (PROM_CLK)
    
    begin
        if rising_edge(PROM_CLK) then
            count <= next_count;
            current_prom_bpi_state <= next_prom_bpi_state;
        end if;
    end process prom_bpi_if_r;
    
    
end architecture rtl;

---

---------------------------
I forgot the "count" signal in the sensitivity list.