error on quartus (10818) with vhdl code

[dorddor]

hi all,
im trying to build a stopper using vhdl, modelsim and quartus.
i wrote the vhdl code and tried it on modelsim and everything was just fine, the compilation and sim were good, as i expected.
when i tried to compile it on quartus it gave me errors. im trying to understand how to fix it for more than 5 hours. please help me.


the errors are:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Dec 23 22:11:21 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopper_new -c stopper_new
Info: Found 2 design units, including 1 entities, in source file stopper.vhd
    Info: Found design unit 1: STOPPER-arc_stopper
    Info: Found entity 1: STOPPER
Info: Found 1 design units, including 1 entities, in source file timer.bdf
    Info: Found entity 1: timer
Info: Elaborating entity "timer" for the top level hierarchy
Warning: Using design file hexss.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: hexss-arc_hexss
    Info: Found entity 1: hexss
Info: Elaborating entity "hexss" for hierarchy "hexss:inst2"
Info: Elaborating entity "STOPPER" for hierarchy "STOPPER:inst"
Warning (10492): VHDL Process Statement warning at stopper.vhd(70): signal "cnt_sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopper.vhd(71): signal "cnt_sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopper.vhd(72): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopper.vhd(73): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopper.vhd(74): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopper.vhd(75): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at stopper.vhd(25): inferring latch(es) for signal or variable "flag", which holds its previous value in one or more paths through the process
Error (10818): Can't infer register for "min[0]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[0]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[1]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[1]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[2]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[2]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[3]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[3]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[4]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[4]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[5]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[5]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[6]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[6]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[7]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[7]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[8]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[8]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[9]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[9]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[10]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[10]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[11]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[11]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[12]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[12]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[13]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[13]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[14]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[14]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[15]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[15]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[16]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[16]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[17]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[17]" at stopper.vhd(25)
Error (10818): Can't infer register for "min[18]" at stopper.vhd(49) because it does not hold its value outside the clock edge
Info (10041): Inferred latch for "min[18]" at stopper.vhd(25)
Error: Can't elaborate user hierarchy "STOPPER:inst"
Error: Quartus II Analysis & Synthesis was unsuccessful. 20 errors, 8 warnings
    Info: Allocated 199 megabytes of memory during processing
    Error: Processing ended: Sun Dec 23 22:11:22 2012
    Error: Elapsed time: 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 20 errors, 8 warnings

and the code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity STOPPER is
    port(CLK, resetN, startN, stopN : in std_logic;
        CNTSEC_units : out std_logic_vector (3 downto 0);
        CNTSEC_tens : out std_logic_vector (3 downto 0);
        SECOND_units : out std_logic_vector (3 downto 0);
        SECOND_tens : out std_logic_vector (3 downto 0);
        MINUTE_units : out std_logic_vector (3 downto 0);
        MINUTE_tens : out std_logic_vector (3 downto 0)
    );
    
end STOPPER;


architecture arc_stopper of STOPPER is
    signal cnt_sec : integer := 0;
    signal sec : integer := 0;
    signal min : integer := 0;
    signal Degel : std_logic; 
begin


process(CLK, resetN, stopN, startN)


variable flag :  integer := 0;
variable cnt_sec_units :  integer := 0;
variable cnt_sec_tens : integer := 0;
variable sec_units : integer := 0;
variable sec_tens : integer := 0;
variable min_units : integer := 0;
variable min_tens : integer := 0;




begin
    if resetN = '0' then 
        cnt_sec     <= 0;
        sec     <= 0;
        min      <= 0;
        flag := 1;
        
    elsif stopN = '0' then
        flag := 1;
    elsif startN = '0' then
        flag := 0;
    end if;
        
    if rising_edge(CLK) then
        if Degel='1' then
            if flag = 0 then    
                if cnt_sec/=99 then
                    cnt_sec <= cnt_sec + 1;
                else                    --cnt_sec=99
                    if sec/=59 then
                        sec <= sec + 1;
                    elsif min/=59 then    --sec=59
                        min <= min + 1;
                        sec <= 0;
                    else                 --sec=59 and min=59
                        min <= 0;
                        sec <= 0;
                    end if;
                    cnt_sec <= 0;
                end if;    
            end if;
        end if;        
    end if;    
    
cnt_sec_units  := cnt_sec mod 10;
cnt_sec_tens  := cnt_sec / 10;
sec_units  := sec mod 10;
sec_tens  := sec / 10;
min_units  := min mod 10;
min_tens  := min / 10;


CNTSEC_units <= conv_std_logic_vector(cnt_sec_units, 4);
CNTSEC_tens <= conv_std_logic_vector(cnt_sec_tens, 4);
SECOND_units <= conv_std_logic_vector(sec_units, 4);
SECOND_tens <= conv_std_logic_vector(sec_tens, 4);
MINUTE_units <= conv_std_logic_vector(min_units, 4);
MINUTE_tens <= conv_std_logic_vector(min_tens, 4);
        
end process;


process (CLK) --CLK process
    variable time : integer range 0 to 500001 := 0;
    constant sec : integer := 5;
    begin
        if rising_edge(CLK) then
            time := time + 1;
            if (time = sec) then 
                time:=0;
                Degel <= '1';
            else 
                Degel <= '0';
            end if;
    end if;
end process;




end arc_stopper;

im a novice with vhdl so i would appreciate any help. thanks

 

[FvM]

Your design doesn't follow the required scheme for synchronous logic synthesis:

if <asynchronous condition> then
  --
elsif <synchronous condition> then -- e.g. rising_edge(clk)
  --
end if;

The synchronous action must be mutual exclusive to all asynchronous actions manipulating a signal.

There are additional problems with (possibly) unintentional latches, but your code would compile at least. In case of doubt, refer to your VHDL text book or the Quartus VHDL templates in the Quartus editor.

 

[dorddor]

i fixed it, but it still error.
but when i change the code:

    if resetN = '0' then 
        cnt_sec     <= 0;
        sec     <= 0;
        min      <= 0;
        flag := 1;
        
    elsif stopN = '0' then
        flag := 1;
    elsif startN = '0' then
        flag := 0;
    end if;
        
    if rising_edge(CLK) then

to:

	if resetN = '0' then 
		cnt_sec 	<= 0;
		sec	 <= 0;
		min 	 <= 0;
		flag := 1;
		
	elsif clk'event and CLK='1' then

the compilation success, but what i need to do with startN and stopN, that what cause the problem, but i cant really delete it, i need it, so what can i do?
thanks

 

[FvM]

You are somehow mixing the problems.

One point is to understand the clear requirements for register synthesis. It demands to have the clock edge sensitive operations mutual exclusive to the asynchronous reset.

But the problem doesn't necessarily affect the start/stop flag because it's only set asynchronously in your code. So it won't cause synthesis errors to keep it asynchronous, e.g. in a different process, or in a separate "if then else" construct.

Another question is if it's reasonable to perform the start/stop action asynchronously? At worst case it can produce unexpected timer results due to timing violations, if the flag state changes near the clock edge. Thus I mean, it should be better done synchronously, which would also avoid your syntax problem.

 

[dorddor]

thank you!