Error obtain in assura Lvs simulation in cadence tool

[pragati raut]

Error obtain in LVS is
1)Rewires
2)nets
3)device
I m sending the screenshot of LVS with error window. Please give us solution for that error.

 

[dick_freebird]

You failed to provide said screen shot, and debugging wants
more than simple displays most likely. Usually it involves you
inspecting the circuit based on the feeble clues the tool
provides and what you know about correct construction.

If you had -a- question, we might answer it. Appears you
have a list of discrepancies that we should solve for free.

And then what will you have learned, that precludes an
infinite series of the same which you won't solve for
yourself either?