Jun 13, 2015 #1 V venkatpasumarthi Newbie level 3 Joined Apr 2, 2015 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 26 Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; entity comp is port(a : in std_logic_vector(7 downto 0); y : out std_logic_vector(7 downto 0)); end comp; architecture dataflow of comp is signal temp: std_logic; begin y<= not(a) + "00000001"; end dataflow; and it is showing the error ** Error: D:/modelsim_projects/2scmpliment.vhd(13): No feasible entries for infix operator "+". Click to expand... Last edited by a moderator: Jun 13, 2015
Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; entity comp is port(a : in std_logic_vector(7 downto 0); y : out std_logic_vector(7 downto 0)); end comp; architecture dataflow of comp is signal temp: std_logic; begin y<= not(a) + "00000001"; end dataflow; and it is showing the error ** Error: D:/modelsim_projects/2scmpliment.vhd(13): No feasible entries for infix operator "+". Click to expand...
Jun 13, 2015 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,419 Helped 14,749 Reputation 29,780 Reaction score 14,099 Trophy points 1,393 Location Bochum, Germany Activity points 298,093 std_logic_vector isn't a numeric data type. No arithmetic operations defined for it. You can use unsigned type instead Or use the non-IEEE library std_arithmetic_unsigned. Or apply type casts like Code: y<= std_logic_vector(unsigned(not(a)) + unsigned("00000001"));
std_logic_vector isn't a numeric data type. No arithmetic operations defined for it. You can use unsigned type instead Or use the non-IEEE library std_arithmetic_unsigned. Or apply type casts like Code: y<= std_logic_vector(unsigned(not(a)) + unsigned("00000001"));