Error message using Modelsim in Linux

[Ciaran]

Hello All

Thank you in advance for kindly agreeing to help me with this, as I have been stuck for quite some time.

Basically, I am receiving the following error message when using Modelsim in Linux:

** Error: (vsim-3601) Iteration limit reached at time 0 ns.

I have read previous articles relating to this particular error message and they suggest that there may be an infinite loop somewhere in my VHDL code causing Modelsim to terminate. I have scanned my code step-by-step and have made changes where I thought the problem might be but nothing has worked so far. The only thing that seems to make any difference is when I change the value of my reset signal in my test bench to '0' initially instead of '1' (See my test bench below). The simulation then runs for 10000 ns before again terminating with the same error message when reset becomes '1'. Can anyone please offer me some alternative explanation as to why this is happening? Thank you again, any suggestions are much appreciated.

Regards

Ciaran


************************************************** *******
--Radix-2 Cell Array Test Bench--

library work;
library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rng_lib.all;
use work.radix2_package.all;

-----------------------------------------------------------------------------------------

entity radix2_cell_array_tb is
end radix2_cell_array_tb;

-----------------------------------------------------------------------------------------

architecture radix2_cell_array_tb of radix2_cell_array_tb is

-----------------------------------------------------------------------------------------

component radix2_cell_array
port(clk :in std_ulogic;
reset :in std_ulogic;
n :in std_ulogic_vector(width downto 0);
b :in std_ulogic_vector(width downto 0);
ain :in std_ulogic;
sum ut std_ulogic_vector(width downto 0));
end component;

-----------------------------------------------------------------------------------------

signal randomnum1 :unsigned(31 downto 0);
signal setofnums1 :std_ulogic_vector(31 downto 0);

signal randomnum2 :unsigned(31 downto 0);
signal setofnums2 :std_ulogic_vector(31 downto 0);

signal randomnum3 :unsigned(31 downto 0);
signal setofnums3 :std_ulogic_vector(31 downto 0);

signal clk :std_ulogic;
signal reset :std_ulogic;
signal n :std_ulogic_vector(width downto 0);
signal b :std_ulogic_vector(width downto 0);
signal ain :std_ulogic;
signal sum :std_ulogic_vector(width downto 0);

-----------------------------------------------------------------------------------------

begin

-----------------------------------------------------------------------------------------

radix2_cell_array_1:radix2_cell_array port map(clk,
reset,
n,
b,
ain,
sum);

-----------------------------------------------------------------------------------------

Clockrocess

begin

loop

clk <= '1';
wait for 5000 ns; --half clock cycle

clk <= '0';
wait for 5000 ns; --half clock cycle

end loop;

end process Clock;

-----------------------------------------------------------------------------------------

RSTrocess

begin

reset <= '1';
wait for 10000 ns; --clock cycle

reset <= '0';
wait;

end process RST;

-----------------------------------------------------------------------------------------

p1rocess(clk,reset)

variable r_uni1 :rand_var;
variable r_uni2 :rand_var;
variable r_uni3 :rand_var;
variable seedA1 :integer := 0;
variable seedB1 :integer := 0;
variable seedC1 :integer := 0;
variable seedA2 :integer := 0;
variable seedB2 :integer := 0;
variable seedC2 :integer := 0;
variable seedA3 :integer := 0;
variable seedB3 :integer := 0;
variable seedC3 :integer := 0;

begin

if reset = '1' then

seedA1 := seedA1 + 231; --change seed
seedB1 := seedB1 + 231; --change seed
seedC1 := seedC1 + 231; --change seed

seedA2 := seedA2 + 101; --change seed
seedB2 := seedB2 + 101; --change seed
seedC2 := seedC2 + 101; --change seed

seedA3 := seedA3 + 83; --change seed
seedB3 := seedB3 + 83; --change seed
seedC3 := seedC3 + 83; --change seed

r_uni1 := init_uniform(seedA1, seedB1, seedC1, 0.0, 100.0);
r_uni2 := init_uniform(seedA2, seedB2, seedC2, 0.0, 100.0);
r_uni3 := init_uniform(seedA3, seedB3, seedC3, 0.0, 100.0);

randomnum1 <= (others => '0');
randomnum2 <= (others => '0');
randomnum3 <= (others => '0');

elsif clk'event and clk = '1' then

r_uni1 := rand(r_uni1);
randomnum1 <= r_uni1.rnd_v;

r_uni2 := rand(r_uni2);
randomnum2 <= r_uni2.rnd_v;

r_uni3 := rand(r_uni3);
randomnum3 <= r_uni3.rnd_v;

end if;

end process p1;

-----------------------------------------------------------------------------------------

setofnums1 <= std_ulogic_vector(randomnum1);
setofnums2 <= std_ulogic_vector(randomnum2);
setofnums3 <= std_ulogic_vector(randomnum3);

ain <= setofnums1(0);
n <= setofnums2(width downto 0);
b <= setofnums3(width downto 0);

-----------------------------------------------------------------------------------------

end radix2_cell_array_tb;
************************************************** *******

 

[aji_vlsi]

Hi Ciaran,
There is nothing wrong in the TB code shown here. Clearly when reset = '1' you have the design coming out of reset and within the design you seem to have that loop. Few choices:

Hello All

The simulation then runs for 10000 ns before again terminating with the same error message when reset becomes '1'. Can anyone please offer me some

I would run the sim till 10000 ns and then do "step" inside GUI. This should reveal the loop though it can be painfully long number of steps - I also wrote a simple TCL proc to do "multiple steps" in VCS/UCLI a while back. Similar thing can be done with MTI as well.

As a last option if you can send a testcase, maybe I can debug it - but that's upto you.


Regards
Ajeetha, CVC
www.noveldv.com

 

[nand_gates]

Checkout with this OR we need to look at code for radix2_cell_array!

--Radix-2 Cell Array Test Bench-- 

library work; 
library ieee; 

use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
use ieee.std_logic_unsigned.all; 
use work.rng_lib.all; 
use work.radix2_package.all; 

----------------------------------------------------------------------------------------- 

entity radix2_cell_array_tb is 
end radix2_cell_array_tb; 

----------------------------------------------------------------------------------------- 

architecture radix2_cell_array_tb of radix2_cell_array_tb is 

----------------------------------------------------------------------------------------- 

  component radix2_cell_array
    port(clk   : in  std_ulogic;
         reset : in  std_ulogic;
         n     : in  std_ulogic_vector(width downto 0);
         b     : in  std_ulogic_vector(width downto 0);
         ain   : in  std_ulogic;
         sum   : out std_ulogic_vector(width downto 0));
  end component;

----------------------------------------------------------------------------------------- 

signal randomnum1 :unsigned(31 downto 0); 
signal setofnums1 :std_ulogic_vector(31 downto 0); 

signal randomnum2 :unsigned(31 downto 0); 
signal setofnums2 :std_ulogic_vector(31 downto 0); 

signal randomnum3 :unsigned(31 downto 0); 
signal setofnums3 :std_ulogic_vector(31 downto 0); 

signal clk :std_ulogic := '0'; 
signal reset :std_ulogic; 
signal n :std_ulogic_vector(width downto 0); 
signal b :std_ulogic_vector(width downto 0); 
signal ain :std_ulogic; 
signal sum :std_ulogic_vector(width downto 0); 

----------------------------------------------------------------------------------------- 

begin 

----------------------------------------------------------------------------------------- 

radix2_cell_array_1:radix2_cell_array port map(clk, 
                                               reset, 
                                               n, 
                                               b, 
                                               ain, 
                                               sum); 

----------------------------------------------------------------------------------------- 
   clk <= transport not clk after 5000 ns;
----------------------------------------------------------------------------------------- 

RST:process 

begin 

reset <= '1'; 
wait for 10000 ns; --clock cycle 

reset <= '0'; 
wait; 

end process RST; 

----------------------------------------------------------------------------------------- 

p1 : process(clk,reset) 

  variable r_uni1 : rand_var;
  variable r_uni2 : rand_var;
  variable r_uni3 : rand_var;
  variable seedA1 : integer := 0;
  variable seedB1 : integer := 0;
  variable seedC1 : integer := 0;
  variable seedA2 : integer := 0;
  variable seedB2 : integer := 0;
  variable seedC2 : integer := 0;
  variable seedA3 : integer := 0;
  variable seedB3 : integer := 0;
  variable seedC3 : integer := 0;

begin

  if reset = '1' then

    seedA1 := seedA1 + 231;             --change seed 
    seedB1 := seedB1 + 231;             --change seed 
    seedC1 := seedC1 + 231;             --change seed 

    seedA2 := seedA2 + 101;             --change seed 
    seedB2 := seedB2 + 101;             --change seed 
    seedC2 := seedC2 + 101;             --change seed 

    seedA3 := seedA3 + 83;              --change seed 
    seedB3 := seedB3 + 83;              --change seed 
    seedC3 := seedC3 + 83;              --change seed 

    r_uni1 := init_uniform(seedA1, seedB1, seedC1, 0.0, 100.0);
    r_uni2 := init_uniform(seedA2, seedB2, seedC2, 0.0, 100.0);
    r_uni3 := init_uniform(seedA3, seedB3, seedC3, 0.0, 100.0);

    randomnum1 <= (others => '0');
    randomnum2 <= (others => '0');
    randomnum3 <= (others => '0');

  elsif clk'event and clk = '1' then

    r_uni1     := rand(r_uni1);
    randomnum1 <= r_uni1.rnd_v;

    r_uni2     := rand(r_uni2);
    randomnum2 <= r_uni2.rnd_v;

    r_uni3     := rand(r_uni3);
    randomnum3 <= r_uni3.rnd_v;

  end if;

end process p1;

----------------------------------------------------------------------------------------- 

setofnums1 <= std_ulogic_vector(randomnum1);
setofnums2 <= std_ulogic_vector(randomnum2);
setofnums3 <= std_ulogic_vector(randomnum3);

ain <= setofnums1(0);
n   <= setofnums2(width downto 0);
b   <= setofnums3(width downto 0);

----------------------------------------------------------------------------------------- 

end radix2_cell_array_tb;

 

[satyakumar]

Hi,
I think in your design, some where process might be used for implimenting combinational blocks. The sensitivity list might be declared wrongly, probably declaring some else block with eg: assign1 <= assign1;.

 

[Ciaran]

Firstly, thank you all for your kind help.

nand_gates, I tried the update you suggested for the test bench but unfortunately this had no effect! I have attached the code for radix2_cell_array. I originally thought that the problem may have been with the Signal_Assign process in which I have a_sig(0) <= a_sig(width+1); carry(0) <= carry(width+1); q_sig(0) <= q_sig(width+1). However, I previously changed the sensitivity list to include a_sig(width+1), carry(width+1), and q_sig(width+1) instead of a_sig, carry, and q_sig but again this had no effect on the error message. So, hopefully someone can see something that I can't in the attached code? Again thanks for your help, I hope to hear from you soon.

Ciaran

*******************************************************************
--Radix-2 Cell Array--

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

use work.radix2_package.all;

-----------------------------------------------------------------------------------------

entity radix2_cell_array is

port(clk :in std_logic;
reset :in std_logic;
n :in std_logic_vector(width downto 0);
b :in std_logic_vector(width downto 0);
ain :in std_logic;
sum ut std_logic_vector(width downto 0));

end radix2_cell_array;

-----------------------------------------------------------------------------------------

architecture radix2_cell_array of radix2_cell_array is

-----------------------------------------------------------------------------------------

component radix2_first_cell
port(clk :in std_logic;
s :in std_logic;
carry ut std_logic_vector(1 downto 0));
end component;

-----------------------------------------------------------------------------------------

component radix2_cell
port(clk :in std_logic;
reset :in std_logic;
s :in std_logic;
n :in std_logic;
b :in std_logic;
qin :in std_logic;
ain :in std_logic;
cin :in std_logic_vector(1 downto 0);
sum ut std_logic;
qout ut std_logic;
aout ut std_logic;
cout ut std_logic_vector(1 downto 0));
end component;

-----------------------------------------------------------------------------------------

signal cnt :integer;
signal sum_in :std_logic_vector(width downto 0);
signal sum_out :std_logic_vector(width downto 0);
signal q_sig :std_logic_vector(width+1 downto 0);
signal a_sig :std_logic_vector(width+1 downto 0);
signal carry :radix2_carry_array;
signal firstcarry :std_logic_vector(1 downto 0);
signal sum_out_collect :std_logic_vector(((cnt_size+1)*(width+1))-1 downto 0);

-----------------------------------------------------------------------------------------

begin

-----------------------------------------------------------------------------------------

Counterrocess(clk,reset)

begin

if reset = '1' then

cnt <= 0;

elsif clk'event and clk = '1' then

if cnt = cnt_size then

cnt <= 0;

else

cnt <= cnt + 1;

end if;

end if;

end process Counter;

-----------------------------------------------------------------------------------------

Collectrocess(clk,reset)

begin

if reset = '1' then

sum_out_collect <= (others => '0');

elsif clk'event and clk = '1' then

for i in cnt_size downto 0 loop

for j in 0 to width loop

if cnt = i then

sum_out_collect((i*(width+1))+j) <= sum_out(j);

end if;

end loop;

end loop;

end if;

end process Collect;

-----------------------------------------------------------------------------------------

Signal_Assignrocess(cnt,ain,firstcarry,sum_out_collect,a_sig,carry,q_sig)

begin

if cnt = 1 then

a_sig(0) <= ain;

carry(0) <= firstcarry;

q_sig(0) <= sum_out_collect(2*(width+1)); --cnt=2--

else

a_sig(0) <= a_sig(width+1);

carry(0) <= carry(width+1);

q_sig(0) <= q_sig(width+1);

end if;

end process Signal_Assign;

-----------------------------------------------------------------------------------------

Sum_Assignrocess(clk,reset)

begin

if reset = '1' then

sum_in <= (others => '0');

elsif clk'event and clk = '1' then

for i in cnt_size-2 downto 1 loop

for j in 0 to width-1 loop

if cnt = i-1 then

sum_in(j) <= sum_out_collect(((i+2)*(width+1))+(j+1));

end if;

end loop;

end loop;

for j in 0 to width-1 loop

if cnt = cnt_size then

sum_in(j) <= sum_out_collect(((2)*(width+1))+(j+1));

end if;

end loop;

for i in cnt_size downto cnt_size-1 loop

for j in 0 to width-1 loop

if cnt = i-1 then

sum_in(j) <= sum_out_collect(((i-(cnt_size-1))*(width+1))+(j+1));

end if;

end loop;

end loop;

if cnt = cnt_size then

sum_in(width) <= '0';

else

for i in cnt_size downto cnt_size-1 loop

if cnt = i-1 then

sum_in(width) <= sum_out_collect(((i-(cnt_size-1))*(width+1)));

end if;

end loop;

for i in cnt_size-2 downto 1 loop

if cnt = i-1 then

sum_in(width) <= sum_out_collect(((i+2)*(width+1)));

end if;

end loop;

end if;

end if;

end process Sum_Assign;

-----------------------------------------------------------------------------------------

radix2_first_cell_1:radix2_first_cell port map(clk,
sum_out_collect(2*(width+1)),
firstcarry);

-----------------------------------------------------------------------------------------

Array_Generate1:for i in width downto 0 generate

radix2_cell_1:radix2_cell port map(clk,
reset,
sum_in(i),
n(i),
b(i),
q_sig(i),
a_sig(i),
carry(i),
sum_out(i),
q_sig(i+1),
a_sig(i+1),
carry(i+1));

end generate Array_Generate1;

-----------------------------------------------------------------------------------------

sum <= sum_out;

-----------------------------------------------------------------------------------------

end radix2_cell_array;
*******************************************************************