vinod.ailsinghani
Newbie level 1
Hi friends,
I have just enrolled to this community.
i am using two EDA tools like Modelsim SE 6.2c and Xilinx 13.2 for verilog RTL coding.
I m getting weird problem in modelsim SE PLUS 6.2c while simulating verilog (i.e. adding signal to wave) code like '# (vish-4014) No objects found matching'? .moreover i also noticed that my main code and test bench are not bounded (unlike in vhdl) whereas same code works or simulated properly on xilinx ISE 13.2 tool? why this is? i am new to verilog language?
however,how to make use of modelsim SE plus 6.2 tool for system verilog (i mean what sort of setting i need to do in tools)?please help me out
regards,
Vinod
I have just enrolled to this community.
i am using two EDA tools like Modelsim SE 6.2c and Xilinx 13.2 for verilog RTL coding.
I m getting weird problem in modelsim SE PLUS 6.2c while simulating verilog (i.e. adding signal to wave) code like '# (vish-4014) No objects found matching'? .moreover i also noticed that my main code and test bench are not bounded (unlike in vhdl) whereas same code works or simulated properly on xilinx ISE 13.2 tool? why this is? i am new to verilog language?
however,how to make use of modelsim SE plus 6.2 tool for system verilog (i mean what sort of setting i need to do in tools)?please help me out
regards,
Vinod