Error loop must terminate within 10,000 iterations (vhdl)

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
 
--
entity InstructionMemory is
    port (
        clk, rst : in std_logic;
        address : in std_logic_vector(31 downto 0);
        instr_out : out std_logic_vector(31 downto 0)
    );
end entity;
architecture aim of InstructionMemory is
 
    type instr_mem is array(0 to 20) of std_logic_vector(31 downto 0);
    signal imem : instr_mem := (others => (others => '0'));
 
begin
    process (clk)
        file file_pointer : text;
        variable line_content : string (1 to 32);
        variable line_num : line;
        variable i : integer := 0;
        variable j : integer := 0;
        variable char : character := '0';
    begin
 
        file_open(file_pointer, "C:/Users/MM/Desktop/PF3/MIPS-Monocycle-32-bits-master/Testcases/instructions.txt", READ_MODE);
        while not endfile (file_pointer) loop -- this is line 31
            readline(file_pointer, line_num);
            READ(line_num, line_content);
 
            for j in 1 to 32 loop
                char := line_content(j);
                if (char = '0') then
                    imem(i)(32 - j) <= '0';
                else
                    imem(i)(32 - j) <= '1';
                end if;
            end loop;
            i := i + 1;
        end loop;
        file_close(file_pointer); -- Close the file
        wait;
    end process;
 
    process (clk, rst)
    begin
        if rst = '1' then
            instr_out <= "00000000000000000000000000000000";
        elsif clk'EVENT and clk = '0' then
 
                assert (( (to_integer(unsigned(address)) mod 4194304)/4) < instr_mem'LENGTH)
                report  "Simulation has ended"
                severity ERROR;
            instr_out <= imem((to_integer(unsigned(address)) mod 4194304)/4);
        end if;
    end process;
end architecture;