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error in vhdl while compiling in vhdl

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goodpranoy

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Error: H:/ollade_latest/datapath_latest_collage.vhd(53): Cannot assign to object "d1" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(54): Cannot assign to object "d2" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(58): VHDL Compiler exiting

i am getting these errors when running the following programs. pls help.
Code:
library ieee;
    use ieee.std_logic_1164.all;
    --use ieee.std_logic_unsigned.all;
    
    entity datapath_latest is
        port(
            D1:in std_logic_vector(7 downto 0);
            D2:in std_logic_vector(7 downto 0);
            Dout:out std_logic_vector(7 downto 0);
            control:in std_logic_vector(2 downto 0);
            load:in std_logic_vector(2 downto 0)
             );
        end datapath_latest;
        
        architecture behav of datapath_latest is
        signal reg_a_data_in : std_logic_vector(7 downto 0 );
        signal reg_b_data_in : std_logic_vector(7 downto 0 );
        signal reg_a_data_out : std_logic_vector(7 downto 0 );
        signal reg_b_data_out : std_logic_vector(7 downto 0 );
        signal a_move : std_logic_vector(7 downto 0 );
        signal b_move : std_logic_vector(7 downto 0 );
        signal d1_signal : std_logic_vector(7 downto 0 );
        signal d2_signal : std_logic_vector(7 downto 0 );
        signal sel_signal : std_logic;  
            
        
component reg_new 

        port( control:in std_logic_vector(2 downto 0);
             data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0));
        end component;


 
component alu_ent
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            reg_a_mov,reg_b_mov:out std_logic_vector(7 downto 0 );
            sel:in std_logic;
            z:out std_logic_vector(7 downto 0)
             );
        end component;
        
        component MUX
            port(
            d0:in std_logic_vector(7 downto 0);
            d1:in std_logic_vector(7 downto 0);
            s:in std_logic;
            y:out std_logic_vector(7 downto 0)
            );
        end component;
        
    begin
    
    mux_a : MUX
    
    port map(
    d0=>a_move,
    d1=>D1,
    s=>sel_signal,
    y=>reg_a_data_in
    );
    
    mux_b : MUX
    
    port map(
    d0=>b_move,
    d1=>D2,
    s=>sel_signal,
    y=>reg_b_data_in
    );
            
    register_a : reg_new
 port map (
            data_in=>reg_a_data_in,
            control=>load,
            data_out => reg_a_data_out
          ) ;
  
  register_b : reg_new
 port map (
           data_in=>reg_b_data_in,
           control=>load,
           data_out => reg_b_data_out
          ) ;
  
  alu:alu_ent
  port map(x=>reg_a_data_out,
           y=>reg_b_data_out,
           z=>Dout,
           reg_a_mov=>a_mov,
           reg_b_mov=>b_mov,
           a=>control,
           sel=>sel_signal
           );
                      
    end behav;

Code:
--mux

library ieee;
    use ieee.std_logic_1164.all;
    entity MUX is
        port(d0,d1:in std_logic_vector(7 downto 0);
            s:in std_logic;
            y:out std_logic_vector(7 downto 0)
            );
        end MUX;
        
        architecture MUX_arch of MUX is
            begin
          process(d0,d1,s)
          begin
                case s is
                     when '0'=>
                      y<=d0;
                     when '1'=> 
                     y<=d1;
                     when others=>
                      y<="ZZZZZZZZ";
                     end case;
     end process;
         end MUX_arch;

Code:
--alu

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity alu_ent is
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            reg_a_mov,reg_b_mov:out std_logic_vector(7 downto 0 );
            sel:in std_logic;
            z:out std_logic_vector(7 downto 0)
             );
        end alu_ent;
        architecture alu_arch of alu_ent is
                 
        
        begin
        process(x,y,a)
        begin
            
            case a is
                when "000"=>
                z<=x+y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "001"=>
                z<=x-y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "010"=>
                reg_a_mov<=y; 
                reg_b_mov<=y;     
                z<="XXXXXXXX";
                sel<='0';
                when "011"=>
                z<=x and y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "100"=>
                z<=x or y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "101"=>
                reg_b_mov<=x;
                reg_a_mov<=x; 
                z<="XXXXXXXX";
                sel<='0';
                
                when others=>
                 z<="XXXXXXXX";
                 reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
            end case;
      end process;
    end alu_arch;

Code:
--register

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity reg_new is
        port( control:in std_logic_vector(2 downto 0);
            data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0)
            );
        end reg_new;
        
    architecture behav of reg_new is
        subtype cell is std_logic_vector(7 downto 0);
        type memarray is array(0 downto 0) of cell;
        signal mem:memarray;
        begin
            process(control)
                      begin
                        
                        case control is
                                                      
                            when "101"=>
                            data_out<=mem(0);
                            when "110"=>
                            mem(0)<=data_in;
                            data_out<=(others=>'Z');
                            when others=>
                            data_out<=(others=>'Z');
                        end case;
            end process;
        end behav;
 

Id have thought the error was self explanitory. You cannot assign to object of mode IN.
 
Id have thought the error was self explanitory. You cannot assign to object of mode IN.

but sir

i have assigned the load and control using portmap.

it is similar to the d1 =>D2 case .
 

The error is not in the code you posted. You must be compiling different files.
 

sir
when i compile the alu program i get this as an error

# Compile of alu_collage.vhd failed with 1 errors.

when i double click to see the error there is no error and i get this.

vcom -work work -2002 -explicit -vopt H:/ollade_latest/alu_collage.vhd
Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity alu_ent
-- Compiling architecture alu_arch of alu_ent
 

thank u sir.
there was another file with the same name.

now it is compiled.
now going to check if it is working as intended.
 

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