Error in VERILOG Code using MODELSIM !!

[Pankaj Dhingra]

I am new to this forum as well as to VERILOG!! I wrote a code for the multiplication of two 8 bit numbers using shift operator and adder ..... i have completed my code but while simulating,I am getting two error and to rectify these errors,I need your help (expert advice) :grin:


this is my code: 1. there are two modules, first one is the TEST-BENCH (stimulus block) followed by my code !!


module multiplication_2_8bit_numbers_tb;

reg [6:0] A,B;
reg Qs,E,X,As,Bs,clk;
reg [12:0] Q;

multiplication_2_8bit_numbers_bhl multiply1 ( a,
as,
b,
bs,
rst,
e,
x,
qs,
q);


initial // intial block to initialise all register to zero
begin
e=0; x=0;qs=0;q=0;clk=0;
end

always
# 5 clk=~clk;

initial
begin
{as,a} = 11_000_101;
{bs,b} = 10_101_010;
end

initial
begin
#80 $display ("{as,a}=%d\n",{as,a});
$display ("{bs,b} =%d\n",{bs,b});
$display ("{qs,q} =%d\n",{qs,q});
end

module multiplication_2_8bit_numbers_bhl (A, //magnitude of first number A
As, // sign bit of first number A
B, // magnitude of second number B
Bs, // sign bit of second number B
rst, // reset
E, // overload (extra bit after addition)
X, // signaling that muliplication is done
Qs, //sign bit of Q(answer after multiplication)
Q); // magnitude of Q

integer i=0;
input As,Bs,rst;
input [6:0] A,B;
output E,X,Qs,Q;
reg Qs,E,X;
reg [12:0] Q;


assign Qs = As ^ Bs; // As e-xor Bs = Qs

always@(rst,posedge clk)
begin //begin of always
if(rst)
{Qs,E,Q} = 0;
else begin // this begin is of else1
for(i=0;i<7;i=i+1)
begin //begin of for loop
if(B==1)
if(i==0) {E,Q}=A;
else begin //begin of else2
A=A<<(i-1);
{E,Q}=A+{E,Q};
end //end of esle2
else
begin //begin of else 3
if(i==0) {E,Q}=0;
else
{E,Q}=(((6+i){0})+({E,Q})); :arrow: // one error is in this line, SYNTAX ERROR ---> UNEXPECTED `{'
end //end of else3
end //end of for looP // multiplication is done
X=1'B1;
end // end of else 1
end //end of always
endmodule // THE END


:arrow: 1 MORE ERROR : error in last line near 'EOF' . unexpected "end of source code"

Thanks in advance!!!

 

[FvM]

The tb module is incomplete. It has to be finished with endmodule before starting a new module. There may be more syntax errors.