[SOLVED] Error in Transmission Code (of UART)

[electrobuz]

I am implementing the Transmission Component to be used in the UART that I want to implement on a Spartan 3E Nexys 2 FPGA board. The code is attached. On simulating, I find that it is not working properly. The 'prescl' counter that counts till 5208 it not being reset to 0 (on checking I found the count does not reach 2600). Any help is appreciated.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


ENTITY TX IS
PORT(
CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
BUSY:OUT STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(7 downto 0);
TX_LINE:OUT STD_LOGIC
);
END TX;



ARCHITECTURE MAIN OF TX IS

SIGNAL PRSCL: INTEGER RANGE 0 TO 5208:=0;
SIGNAL INDEX: INTEGER RANGE 0 TO 9:=0;
SIGNAL DATAFLL: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL TX_FLG: STD_LOGIC:='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(TX_FLG='0' AND START='1')THEN
TX_FLG<='1';
BUSY<='1';
DATAFLL(0)<='0';
DATAFLL(9)<='1';
DATAFLL(8 DOWNTO 1)<=DATA;
END IF;

IF(TX_FLG='1')THEN
IF(PRSCL<5207)THEN
PRSCL<=PRSCL+1;
ELSE
PRSCL<=0;
END IF;

IF(PRSCL=1111)THEN
TX_LINE<=DATAFLL(INDEX);
IF(INDEX<9)THEN
INDEX<=INDEX+1;
ELSE
TX_FLG<='0';
BUSY<='0';
INDEX<=0;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END MAIN;

 

[aruipksni]

I am implementing the Transmission Component to be used in the UART that I want to implement on a Spartan 3E Nexys 2 FPGA board. The code is attached. On simulating, I find that it is not working properly. The 'prescl' counter that counts till 5208 it not being reset to 0 (on checking I found the count does not reach 2600). Any help is appreciated.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


ENTITY TX IS
PORT(
CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
BUSY:OUT STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(7 downto 0);
TX_LINE:OUT STD_LOGIC
);
END TX;



ARCHITECTURE MAIN OF TX IS

SIGNAL PRSCL: INTEGER RANGE 0 TO 5208:=0;
SIGNAL INDEX: INTEGER RANGE 0 TO 9:=0;
SIGNAL DATAFLL: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL TX_FLG: STD_LOGIC:='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(TX_FLG='0' AND START='1')THEN
TX_FLG<='1';
BUSY<='1';
DATAFLL(0)<='0';
DATAFLL(9)<='1';
DATAFLL(8 DOWNTO 1)<=DATA;
END IF;

IF(TX_FLG='1')THEN
IF(PRSCL<5207)THEN
PRSCL<=PRSCL+1;
ELSE
PRSCL<=0;
END IF;

IF(PRSCL=1111)THEN
TX_LINE<=DATAFLL(INDEX);
IF(INDEX<9)THEN
INDEX<=INDEX+1;
ELSE
TX_FLG<='0';
BUSY<='0';
INDEX<=0;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END MAIN;

first your suppose to put your code with a vhdl header.
second your counter should have range of 0 to 2**n -1 , when n is natural number.
in this case 0 to 8191
also you only count up to 5207 so you can't reach 5208.

 

[ads-ee]

I ran the following commands in modelsim and the PRSCL value goes past the count of 2600 and rolls over at 5207 back to 0.

force CLK 0,1 10 ns -repeat 20 ns
force START 0, 1 100 ns
force DATA 16#56
run 300 us

Results in the following output.


Regards

 

[electrobuz]

I ran the following commands in modelsim and the PRSCL value goes past the count of 2600 and rolls over at 5207 back to 0.

force CLK 0,1 10 ns -repeat 20 ns
force START 0, 1 100 ns
force DATA 16#56
run 300 us

Results in the following output.
View attachment 96591

Regards

Hey,
I wanted to confirm something about your simulation.
1.The CLK has a period of 10ns
2.Start is made 1 after 100ns
3.Running for 300ns

Firstly what happens when you do this force DATA 16#56 ?
Result of my simulation:


Here my PRSCL and Index have ridiculous values.

 

[ads-ee]

1. The clock has a period of 20 ns, which was arbitrary, since I had no idea what the clock frequency was supposed to be. Besides it doesn't matter for a functional check.
2. yes it's also aligned with the falling edge to make it easy to see that it 3was seen on the next rising edge of CLK.
3. No 300 us not ns.

I didn't care about the data, nothing in the simulation control for PRSCL was dependent on the data, so I just forced it to a single value of 0x56 '16#' signifies that the values following the # are hex digits.

You've got the simulation zoomed in so much I can't make out anything as you've only got 5 ps of waveforms showing. The value of PRSCL seems reasonable as it's 2327 decimal and the index is 4 decimal. Nothing wrong there...

Well you know...
There are 10 types of people, those who understand binary and those who don't. ;-)

Regards,

 

[electrobuz]

ads-ee,
I totally missed the fact that PRESCL and INDEX are values in binary and considered them to be as integers (since they were defined as integer signals) and got frustrated by seeing those arbitrary 'int' values.
It seems to be working fine now having checked it again.
P.S I think I will never forget to think in binary again (atleast after this embarrassment )

Thanks