error in the following vhdl prog????

[velu.plg]

k thanks ....

i do what u say...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
use ieee.numeric_std;
--use ieee.std_logic_arith.all;

entity adc is
port(clk:in std_logic;a:in std_logic_vector(15 downto 0);voutut real);
end adc;

architecture a_body of adc is

begin

process(clk)
begin
if(clk='1')then
Vout <= (3.3 * ((real((to_integer(unsigned(a)))) / 65535.0)));
end if;
end process;

end a_body;

but still i have one problem......

** Error: D:/project files/wsn and prng/foldedtree.vhd(19): Illegal type conversion from ieee.std_logic_1164.std_logic_vector to ieee.numeric_bit.unsigned (array element type difference).
** Error: D:/project files/wsn and prng/foldedtree.vhd(23): VHDL Compiler exiting

 

[aruipksni]

k thanks ....

i do what u say...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
use ieee.numeric_std;
--use ieee.std_logic_arith.all;

entity adc is
port(clk:in std_logic;a:in std_logic_vector(15 downto 0);voutut real);
end adc;

architecture a_body of adc is

begin

process(clk)
begin
if(clk='1')then
Vout <= (3.3 * ((real((to_integer(unsigned(a)))) / 65535.0)));
end if;
end process;

end a_body;

but still i have one problem......

** Error: D:/project files/wsn and prng/foldedtree.vhd(19): Illegal type conversion from ieee.std_logic_1164.std_logic_vector to ieee.numeric_bit.unsigned (array element type difference).
** Error: D:/project files/wsn and prng/foldedtree.vhd(23): VHDL Compiler exiting

put in comment :

--use ieee.numeric_bit.all;

 

[FvM]

Looks like you are choosing libaries by try and error.

After commenting ieee.numeric_bit there are still incompatible libraries. You should use true IEEE libraries only:

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

The code can be only used for simulation purposes, e.g. a hardware model in a testbench, because the real type isn't synthesizable.

Did you mean to make a latch here

if(clk='1')then