Error in synthesis with Precision RTL

[shakeebh]

precision rtl synthesis combinatorial loop

Hello everyone

I am trying to synthesize the following code with Precision RTL synthesis 2005b.91 but the synthesis fails with the following error:

Some input to a binary operator is directly connected to its output -- ifhs1_rh1_ix1

here is the verilog code of the asynchronous state machine:

module rst_handler(fwd_rst, rst, clk);

output fwd_rst;
input rst, clk;

parameter s0 = 3'b011, s1 = 3'b001, s2 = 3'b010, s3 = 3'b110,
d1 = 3'b111, d2 = 3'b0;

reg [2:0] n_state;
reg fwd_rst;
wire [2:0] p_state;

assign p_state = n_state;

always @ (p_state or clk or rst) begin
n_state = s0;
fwd_rst = 0;
if (rst) begin
if (p_state == s0) begin
if (clk)
n_state = s1;
if (!clk)
n_state = s2;
end
if (p_state == s1) begin
if (clk)
n_state = s1;
if (!clk)
n_state = d2;
end
if (p_state == s3) begin
fwd_rst = 1;
n_state = s3;
end
if (p_state == d2) begin
n_state = s2;
end
end
end
endmodule

I will appreciate if someone can point me a way out of this problem.

Thanks

 

[a_bohlooli]

Error in synthesis

hi
you used clk signal incorrectly. you should use neg or pos edge of clk not both in always

 

[gliss]

Re: Error in synthesis

always @ (p_state or clk or rst) begin

Is that synthesizable?

 

[Mr.Anonymous]

Error in synthesis

I suppose you have combinatorial loop on this _asynchronous_ design.