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error in shift operator in vhdl

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Mkanimozhi

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vhdl shift

need simple code in vhdl using shift opeartors
buz
here is my code , but i m getting error

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:41:21 12/22/2008
-- Design Name:
-- Module Name: sll_op - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sll_op is
port(
a: in std_logic_vector(4 downto 0);
b: out std_logic_vector(4 downto 0));
end sll_op;

architecture Behavioral of sll_op is
begin
b<= a srl 1;
end Behavioral;


thanks in advance
kanimozhi.m
 

vhdl shift operator

You are using a numeric_std shift function, that isn't defined for std_logic_vector.

Generally, it most likely doesn't make sense to mix incompatible numeric libraries. In any case, if using libraries, it's necessary to learn about the available library functions and the applicable types.

Another option is avoid library functions in this case and write explicitely what you want:
Code:
b <= '0' & a(4 downto 1);
 

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