[SOLVED] ERROR:HDLParsers:164 " Line 38. parse error,

[chaitanya.531]

Hey Folks,
plz
Need a little help here with my VHDL code.

I'm new to VHDL so please bear with me.

I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
When I run check syntax, the following is displayed:
Compiling vhdl file "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" in Library work.
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 38. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 39. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 40. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 41. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 42. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 49. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 50. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 51. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 52. parse error, unexpected WHEN, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 53. parse error, unexpected WHEN, expecting SEMICOLON

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity circularshift is  port (
        sn     : in  std_logic_vector(5 downto 1);  -- number of rotate steps
        di     : in  std_logic_vector(32 downto 1);  -- data in 
        encdec : in std_logic ;                  -- enc or dec 
        do     : out std_logic_vector(32 downto 1)   -- data out
    );
end circularshift;

architecture Behavioral of circularshift is
    signal d0 : std_logic_vector(32 downto 1);
    signal d1 : std_logic_vector(32 downto 1);
    signal d2 : std_logic_vector(32 downto 1);
    signal d3 : std_logic_vector(32 downto 1);
    signal d4 : std_logic_vector(32 downto 1);
    signal r1 : std_logic_vector(32 downto 1);
    signal r2 : std_logic_vector(32 downto 1);
    signal r4 : std_logic_vector(32 downto 1);
    signal r8 : std_logic_vector(32 downto 1); 
    signal d5  : std_logic_vector(32 downto 1);
    signal r16 : std_logic_vector(32 downto 1); 
begin 
p1 : process (encdec)
begin

if  encdec <= '1' then

    r1  <= d0(32-1  downto 1) & d0(32);
    r2  <= d1(32-2  downto 1) & d1(32 downto 32-1);
    r4  <= d2(32-4  downto 1) & d2(32 downto 32-3);
    r8  <= d3(32-8  downto 1) & d3(32 downto 32-7); 
    r16 <= d4(32-16 downto 1) & d4(32 downto 32-15); 
    d0 <= di;
    d1 <= r1  when (sn(1)='1') else d0;
    d2 <= r2  when (sn(2)='1') else d1;
    d3 <= r4  when (sn(3)='1') else d2;
    d4 <= r8  when (sn(4)='1') else d3; 
    d5 <= r16 when (sn(5)='1') else d4; 
    do <= d5; 
else
    r1  <= d0(1) & d0(32 downto 2 );
    r2  <= d1(2  downto 1) & d1(32 downto 3);
    r4  <= d2(4  downto 1) & d2(32 downto 5);
    r8  <= d3(8  downto 1) & d3(32 downto 9); 
    r16 <= d4(16 downto 1) & d4(32 downto 17); 
    d0 <= di;
    d1 <= r1  when (sn(1)='1') else d0;
    d2 <= r2  when (sn(2)='1') else d1;
    d3 <= r4  when (sn(3)='1') else d2;
    d4 <= r8  when (sn(4)='1') else d3; 
    d5 <= r16 when (sn(5)='1') else d4; 
    do <= d5; 

end if;

end process;
end Behavioral;

 

[graphene]

this is unsythesizable... the condition made using "when" has no legal significance although it appears to have one... so use clock condtions or rewrite the when statemtns differently... am sure if u sort it u ll get d solution in 2 mins.. i foudn it.. but u try it yrself..

 

[TrickyDicky]

"when" has to be used outside a process

 

[graphene]

TrickyDicky... dats exactly correct... i wanted d person to learn dat him/herself...

 

[chaitanya.531]

this is unsythesizable... the condition made using "when" has no legal significance although it appears to have one... so use clock condtions or rewrite the when statemtns differently... am sure if u sort it u ll get d solution in 2 mins.. i foudn it.. but u try it yrself..

ya igot
thank u