Error during Modelsim simulation * Error: (vsim-3053)

[roy_ece]

Error during simulation

Hi,
I am getting the following error in Modelsim. Can anyone help me fix this .
* Error: (vsim-3053) C:/lcm/Tb_LCM.v(42): Illegal output or inout port connection (port 'LCMo').
Thanks ,
Regards,
henry

 

[sudhirkv]

Re: Error during simulation

How u have declared the port LCMo

can u just paste u code here

 

[roy_ece]

Re: Error during simulation

The LCM calculator is a sequential circuit.
It takes 5 inputs:
• a Clock (Clk),
• a Reset (Rst),
• the first number (A) is unsigned and less than 255
• the second number (B) is also unsigned and less than 255, and
• an enable(En) signal that starts the computation.
It has 3 outputs:
• the computed LCM number (LCM)
• a signal that is asserted when the computation is completed (Done) and
• overflow signal that is asserted when the computed lcm can’t be represented by the unit's
vector width (Overflow).
The following is a suggestion for an algorithm:
1. Pick the larger of the two numbers.
2. Then generate multiples of this number by using an Adder.
3. Every multiple is then divided by the smaller number to see if the remainder is zero.
4. If the remainder is zero, then the adder output is the LCM, assert Done.
5. If the remainder is not zero, try again by generating a new multiple (i.e. by adding the
number to the accumulated adder output).
6. If the LCM could not be computed and the adder output overflows, assert the Done
signal and generate an Overflow exception.
///////////////////////////////////////////////////
///////Verilog Design for LCM block////////////////
///////////////////////////////////////////////////

///start up simluation for verilog design by setting
///timescale
`timescale 1ns / 1ns

//module Description
module LCM( LCMo, Done, Overflow, A, B, En, Clk, Rst);
//parameter n = 5 ;
output [3] LCMo ;
output Done, Overflow;
//output [3] counter;
input [3] A, B;
input En, Clk, Rst;

//declaration of any variable assigned within always@block
reg [3] LCMo ;
reg Overflow;
reg [3] Dividend;
reg [3] Divisor;
reg [3] Adder = 0 ;
//reg Done;
//reg [3] add;
wire Done;
// changed counter from reg to wire
//wire [3] counter;
wire [3] Remainder;
//reg [3] acc;
//Proceedure block for finding the greatest of the two numbers

always@(posedge Clk or posedge Rst )
begin
// check for Synchronous Reset
if(Rst)
begin
Dividend<= 0;
Divisor<= 0;
end
else
// Assigning largest of A,B to Dividend
// and smallest to Divisor
if(En)
begin
// add <= Adder;
if (A>B)
begin
Dividend <= A;
Divisor <= B;
end
else
begin
Dividend <= B;
Divisor <= A;
end
end
end

//Performing division
DIVISION u0 ( ,Remainder, Done, Error, Dividend,Divisor,Clk,Rst,En);

//proceeedure for Generating multiples of Dividend
//always@( Dividend or Error or Adder or Done or Remainder)
//changed
always@(Done or Rst or Dividend)
begin
if(Rst)
Adder = 0;
else
if( Done)
Adder = Dividend;
else
Adder = Adder + Dividend;
end

//proceedure for assigning outputs

always@(Remainder or Adder or Error)
//checking if remainder is zero then Done is asserted
begin
if (Remainder )
begin
LCMo = 0;
Overflow = 0;
end
// if LCM cannot be computed then assert Overflow
else
begin
LCMo = Adder;
Overflow = ~Error;
end
end
endmodule

//////////////////////////////////////////////////////////////
// Verilog Design for a 4 bit Division block which generates/////
// 4 bit remainder and quotient ////
////////////////////////////////////////////////////////////
//
// start up every verilog design by
// setting up the time scate for simulation
`timescale 1ns / 1ns

// module description

module DIVISION( Quotient, Remainder, Done, Error, Divident, Divisor, clk, RST, Divide);
parameter n =5;
//output [(n-2)] counter;
output [(n-2)] Quotient, Remainder;
output Done, Error;
input [(n-2)] Divident;
input [(n-2)] Divisor;
input clk, RST, Divide;
// declare any variable assigned within an always@ block as a reg
reg Done, Error;
reg [(n-2)] A;
reg [(n-2)] B;
//reg [(n-2)] P;
// orig: reg [2*n-3] PA
// 1 bit is taken to be extra for preventing overflow
reg [2*n-2] PA;
reg [(n-2)] counter;


//Proceedural block to design a division block with enable signal
//called divide along with clock to generate remainder along with quotient
// and as well generate flag outputs Done to indicate done operation
//and Error if unable to compute division.


always@(posedge clk or posedge RST)
begin

//check for reset signal
if (RST)
begin
// orig: P <= 4'b0000;
PA <= 0;
Done <= 0;
// orig: Error <= 1
Error <= 0;
counter <= 0;
end
else
//check for enable signal divide
if (Divide)
begin
// assign Divident and Divisor to register variable A and B respectively.
// orig: P [(n-2)] <= 4'b0000;
// orig: A [(n-2)] <= Divident [(n-2)];
// orig: B [(n-2)] <= Divisor [(n-2)];
A <= Divident;
B <= Divisor;
// Append Divident to 8 bit register PA
// orig: PA <= {P[(n-2)], Divident[(n-2)]};
PA <= A;
//initialize counter to zero value
// counter <= upperlimit(n-2);
if ( A>B)

begin
counter <= 1;
Done <= 0;
if(counter>=1 & counter <= (n-1))
begin
//if the value of PA[6] is lessthan B, then left shift by 1 bit.
//and append zeroto the Lsb of PA.
if(PA[2*n-4n-2)] < B)
begin
PA[2*n-2] <= 0;
PA[2*n-3n-4)] <= PA[2*n-4n-5)];
PA[n-5] <= 0;

end
else
// if the value of PA[6] is greater than or equalto B, then left
// shift by 1 bit and substract B from PA[6] and set to PA[6]
//and append one to the Lsb of PA.
// if(PA[2*n-4n-2)] >= B[(n-2)])
begin
PA[2*n-2n-1)] <= {1'b0,PA[2*n-4n-2)]} - {1'b0,B};
PA[(n-2)n-5)] <= {PA[(n-3)], 1'b1};
PA[2*n-2] <= 0;

//PA[(n-2)n-4)] <= PA[(n-2)];
//PA[n-5] <= 1;
end
//Increment the counter
counter <= counter +1 ;
Done <= 0;
Error <= 0;
end

//else
if (counter == (n-1))
Done <= 1;

end
else if(A<B)
begin Error <= 1; Done<= 1; end
else if(A==B)
begin Error <=0 ; Done <= 1; end


end

end
// assigning back the Reminder and Quotient values
assign Remainder [(n-2)] = PA [2*n-3:n-1] ;
assign Quotient [(n-2)] = PA [(n-2)];
endmodule

Added after 1 minutes:

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[sudhirkv]

Re: Error during simulation

I guess u have pasted the wrong code

this code with module LCM is compiling properly.

Send me the test bench code. problem is there only i guess

 

[devas]

Re: Error during simulation

Hi,

I get another error in Modelsim:
Error: C:/Temp/tmp.v('8'): Packed dimension must specify a range.
The same error exists for all bus input/outputs.

This error can be solved by specifying also the LSB range:
output [3:0] LCMo;

In Verilog you normally specify the MSB and LSB range of a bus signal.

Devas

 

[sudhirkv]

Re: Error during simulation

Yes,

The range of the vector must be defined clearly

u cannot have a variable for that.