Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Error during ISE Translate process in UCF file

Status
Not open for further replies.

dpaul

Advanced Member level 5
Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,851
Helped
317
Reputation
635
Reaction score
352
Trophy points
1,373
Location
Germany
Activity points
13,399
I am doing the ISE Implement process for the 1st time and am stuck in the Translate step.

The input is an edf file generated by Synplify flow and using the ucf file, I am trying to do an implementation.

In the top level there is clock PLL Xilinx Coregen module instiantiated.
Code:
clk_wiz_v3_6 clk_wiz_v3_6_inst
	 (// Clock in ports
	  .CLK_IN1  		  (USB_IFCLK_pin),// IN 48 Mhz 
	  // Clock out ports
	  .CLK_OUT1 		  (usb_clk),	 // OUT 48 MHz clock
	  .CLK_OUT2 		  (clk),	     // OUT 24 MHz clock
	  .CLK_OUT3 		  (clk_180),	 // OUT 24 MHz clock, 180 deg
	  // Status and control signals
	  .RESET			  (sys_rst),     // IN
	  .LOCKED			  (locked));     // OUT

Now there is a constraint in the ucf file,
NET clk_wiz_v3_6_inst/usb_clk PERIOD = 20833 ps;

For the above ucf file entry, ISE Translate process is reporting the following error:
ERROR:ConstraintSystem:59 - Constraint <NET clk_wiz_v3_6_inst/usb_clk
PERIOD = 20833 ps;> [te0630_top.ucf(80)]: NET "clk_wiz_v3_6_inst/usb_clk" not
found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

I don't understand the above error because clk_wiz_v3_6_inst is being instiantiated in my top-module and I have triple checked for spelling mistakes.

Any suggestions why this is happening?
 

I suppose it is complaining about USB_CLK not being present within the clk instance...
 

Hi,
I found the reason why ISE is giving such an error but I don't know how to fix it.

After checking the EDF file manually, I found that there is no connection defined for "usb_clk" in the clk_wiz_v3_6_inst (all other wire connections for this instance I can clearly see).
Since in the RTL top-level design file the connection exists, but in the EDF file it doesn't, so one possible explanation for this might be that synthesis is optimizing out this connection.

Is there any way of specifying in the Synplify input file by way of TCL command not to optimize this connection?

Other hypothesis for this problem is also welcome!
 

Try to set a "keep" attribute on the net in the VHDL or verilog source file.
 

"NET clk_wiz_v3_6_inst/usb_clk " would refer to a "usb_clk" within clk_wiz_v3_6_inst. The clock name is probably "usb_clk". In the extreme case, you can do a build without timing constraints just to see what the tools come up with for net names.
 

Yes, for Synplify, /* keep_syn=1 */ works if used in the RTL.
I also fixed my top-level design and now there are no problems.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top