Apr 28, 2021 #1 T TH22 Newbie Joined Jul 23, 2020 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 35 Hello, I have a question about synthesis in Design Vision. After synthesis the VHDL source code in Design Vision I got the following error: "Error: Value for list 'source_objects' must have 1 elements. (CMD-036)" Click to expand... How can I fix the issue? Thanks in advance.
Hello, I have a question about synthesis in Design Vision. After synthesis the VHDL source code in Design Vision I got the following error: "Error: Value for list 'source_objects' must have 1 elements. (CMD-036)" Click to expand... How can I fix the issue? Thanks in advance.