[SOLVED] error: can't defined "/" operator

[fanwel]

Hello everyone,

Here is my code where I want to add two values of a vector. For example, I have a vector (3,4) and I want to do like this;
(3+4)/2;

Package my_data_types is
Type vector is array (1 downto 0) of integer;
Type vector_next is array (0 downto 0) of integer;
End my_data_types;

LIBRARY ieee;
USE ieee.ALL;
USE work.my_data_types.all;

ENTITY adddiv IS
PORT (
Ra : IN vector;
clk : IN bit;
A : OUT vector_next
);
END adddiv;

ARCHITECTURE adddiv OF adddiv IS
BEGIN
Process(clk)
variable temp: vector_next;
BEGIN
If clk'event and clk = '1' Then
temp := ((Ra(0) + Ra(1))/2);
End if;
A <= temp(0 downto 0) after 20ns;
END PROCESS;
END adddiv;

But, this error occur:

Error (10327): VHDL error at adddiv.vhd(24): can't determine definition of operator ""/"" -- found 0 possible definitions

Can anyone help me..many thanks

 

[kalyanasv]

the problem with that is division is not readily synthesizable. So you have a couple of options:
Instead of doing a temp := ((Ra(0) + Ra(1))/2); you can shift right by 2 i.e. srl(Ra(0)+Ra(1)).

Or instead of division you can do multiple subtractions
**broken link removed**

or with synopsys use DW_Div

**broken link removed**

or well you can also use: sra (arthimetic right shift)

 

[TrickyDicky]

kaltanasv - you havent looked at the types! Plus "/" is very synthesisable, especially for 2^n.

fanwell - the problem is because there is no "/" operator for the vector_next type. try this instead:

temp(0) := ((Ra(0) + Ra(1))/2);

O also assume this is just a model, because
A <= temp(0 downto 0) after 20ns;

is not synthesisable - the delay will be ignored when you compile.

 

[fanwel]

Hi kalyanasv,

It is same division operation with shifter operation?
Your link given above was expired, can you give back..
Thanks for reply

---------- Post added at 04:25 ---------- Previous post was at 03:57 ----------

Hi TrickyDicky,

I solve the problem with your help..Many thanks

 

[kalyanasv]

Hi,

Trickydicky: your right.

Fanwei: considering you only operating on integers and not std_logic_vectors you are better off using "/" operator as prescribed above.

you could also try sra, srl..which all pretty much give you the same thing.

 

[TrickyDicky]

But you cannot do sra and srl on integers.

Plus why would you do any arithmatic on std_logic_vectors? you need signed/unsigned for arithmatic