dksagra
Junior Member level 1
Hi,
i have made one project in simulink (.mdl)
just a 2x2 matrix multiply
i used xilinx blockset toolbox for making 2x2 matirx multiply with the help of muliplier, add/subs, convert,gateway blocks etc.
actually i am making a 32 bit width 2x2 matrix multiplier..
In model block of 2x2 matrix muliply ,the arrangement (connection of all individual blocks) is same like i mentioned below.
in--->gateway in-->convert(32 bit, signed, decimal at 16)-->mult-->add-->convert-->gateway out--> out and display.
compilation is perfectely happening and results is coming and accurate.
when i generate VHD code of it and sysnthesis and i go for the systhesis report, it is generating everthing good (i.e. LUT,FF, SLICE etc used) but with having high IOB (44 %)
for the same example when i reduce number of bits to 16 bits, signed and decimal at 8 and did the same procedure again now everything remain same but IOB used got decrease(22 %)
for the same example when i reduce number of bits to 8 bits, signed and decimal at 4 and did the same procedure again still everything remain same but IOB used further decrease.(11 %)
though IOB are decreasing but still they are utilizing more resources in FPGA
why this is happening?
is there any way to improve my mdl block diagram so i can sought out the problem of IOB utilization
i have made one project in simulink (.mdl)
just a 2x2 matrix multiply
i used xilinx blockset toolbox for making 2x2 matirx multiply with the help of muliplier, add/subs, convert,gateway blocks etc.
actually i am making a 32 bit width 2x2 matrix multiplier..
In model block of 2x2 matrix muliply ,the arrangement (connection of all individual blocks) is same like i mentioned below.
in--->gateway in-->convert(32 bit, signed, decimal at 16)-->mult-->add-->convert-->gateway out--> out and display.
compilation is perfectely happening and results is coming and accurate.
when i generate VHD code of it and sysnthesis and i go for the systhesis report, it is generating everthing good (i.e. LUT,FF, SLICE etc used) but with having high IOB (44 %)
for the same example when i reduce number of bits to 16 bits, signed and decimal at 8 and did the same procedure again now everything remain same but IOB used got decrease(22 %)
for the same example when i reduce number of bits to 8 bits, signed and decimal at 4 and did the same procedure again still everything remain same but IOB used further decrease.(11 %)
though IOB are decreasing but still they are utilizing more resources in FPGA
why this is happening?
is there any way to improve my mdl block diagram so i can sought out the problem of IOB utilization
